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Rws dev #35

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Rws dev #35

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Hi Richard,
This update implements a few key items:
1)Creates a variable timeout in the Wire library, along with the associated Reset capability
2) Implements the reset in the IMX code to bitbang the clock until both sda and scl go high again
3) Changes the CLKLO value for the default master from 37 to 42 which works great for the AIF device. I was not sure how best to implement this and whether it makes sense to make it global, and if not how to override effectively in a specific implementation.
4) Fixed bug where address NAK was reported as DATA NAK. This bug fix is not perfect (basically looks if there are still items in the TX queue). but probably good?

- lots of debug statements enabled
- Added configurable timeout
- Added setWireTimeout command
- Added a reset to unstick a stuck i2c
- Added a reset function to the IMX code, as well as the driver library, and the Wire library
- Added standard Arduino setWireTimout function.  Including automatic Reset code function .
- Updated CLKLO default Bus Master configuration to be 42 rther than 37 to deal with an issue on ACK/NACK timing for Artesyn AIF06 devices.
- Fixed bug were a NAK on the address transmission was incorrectly reported as a DATA Nak rather than an Address NAK
- Added additional debug print statements
- Fixed cleanup when NAK and also around PLTF processing
- Made sure that on abort the transmit and receive queues are empty.
- Reset function does a bitbang of the clock pin until lines go high
- made consistent debug messages with micros first, then more detail so easy to track transitions over time
- Remove Abort on fifos not empty, just clears the fifo's and moves on
- removed sending STOP on arbitration lost as we will reset anyways
- on FEF do a reset
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