added some missing ARM flags/regs

trailofbits · Dec 7, 2022 · 58733a7 · 58733a7
1 parent ad19ca5
commit 58733a7
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Showing 3 changed files with 57 additions and 3 deletions.
diff --git a/src/arch/arch_ARM32.cpp b/src/arch/arch_ARM32.cpp
@@ -40,7 +40,20 @@ namespace ARM32
             {"ZF", ZF},
             {"CF", CF},
             {"VF", VF},
-            {"QF", QF}
+            {"QF", QF},
+
+            {"JF", JF},
+            {"GE1", GE1},
+            {"GE2", GE2},
+            {"GE3", GE3},
+            {"GE4", GE4},
+            {"TF", TF},
+
+            {"tmpNG", tmpNG},
+            {"tmpZR", tmpZR},
+            {"tmpCY", tmpCY},
+            {"tmpOV", tmpOV},
+            {"SC", SC}  //shift_carry
         };
     }
 
@@ -71,6 +84,17 @@ namespace ARM32
             case CF:
             case VF:
             case QF:
+            case JF:
+            case GE1:
+            case GE2:
+            case GE3:
+            case GE4:
+            case TF:
+            case tmpNG:
+            case tmpZR:
+            case tmpCY:
+            case tmpOV:
+            case SC:
                 return 8;
             default:
                 throw runtime_exception("ArchARM32::reg_size(): got unsupported reg num");

diff --git a/src/include/maat/arch.hpp b/src/include/maat/arch.hpp
@@ -457,7 +457,20 @@ namespace ARM32
     static constexpr reg_t VF = 20;
     static constexpr reg_t QF = 21;
 
-    static constexpr reg_t NB_REGS = 22;
+    static constexpr reg_t JF = 22;
+    static constexpr reg_t GE1 = 23;
+    static constexpr reg_t GE2 = 24;
+    static constexpr reg_t GE3 = 25;
+    static constexpr reg_t GE4 = 26;
+    static constexpr reg_t TF = 27;  //thumb-bit (TB)
+
+    static constexpr reg_t tmpNG = 28;
+    static constexpr reg_t tmpZR = 29;
+    static constexpr reg_t tmpCY = 30;
+    static constexpr reg_t tmpOV = 31;
+    static constexpr reg_t SC = 32;  //shift_carry
+
+    static constexpr reg_t NB_REGS = 33;
 
      /** \addtogroup arch
      * \{ */

diff --git a/src/third-party/sleigh/native/reg_translator.cpp b/src/third-party/sleigh/native/reg_translator.cpp
@@ -1424,9 +1424,26 @@ maat::ir::Param sleigh_reg_translate_ARM32(const std::string& reg_name) {
     if (reg_name == "sp") return maat::ir::Reg(maat::ARM32::SP, 32);
     if (reg_name == "lr") return maat::ir::Reg(maat::ARM32::LR, 32);
     if (reg_name == "pc") return maat::ir::Reg(maat::ARM32::PC, 32);
-
+    
     if (reg_name == "cpsr") return maat::ir::Reg(maat::ARM32::CPSR, 32);
 
+    if (reg_name == "NG") return maat::ir::Reg(maat::ARM32::NF, 8);
+    if (reg_name == "ZR") return maat::ir::Reg(maat::ARM32::ZF, 8);
+    if (reg_name == "CY") return maat::ir::Reg(maat::ARM32::CF, 8);
+    if (reg_name == "OV") return maat::ir::Reg(maat::ARM32::VF, 8);
+    if (reg_name == "Q") return maat::ir::Reg(maat::ARM32::QF, 8);
+    // if (reg_name == "J?") return maat::ir::Reg(maat::ARM32::JF, 8);
+    if (reg_name == "GE1") return maat::ir::Reg(maat::ARM32::GE1, 8);
+    if (reg_name == "GE2") return maat::ir::Reg(maat::ARM32::GE2, 8);
+    if (reg_name == "GE3") return maat::ir::Reg(maat::ARM32::GE3, 8);
+    if (reg_name == "GE4") return maat::ir::Reg(maat::ARM32::GE4, 8);
+    if (reg_name == "TB") return maat::ir::Reg(maat::ARM32::TF, 8);
+    if (reg_name == "tmpNG") return maat::ir::Reg(maat::ARM32::tmpNG, 8);
+    if (reg_name == "tmpZR") return maat::ir::Reg(maat::ARM32::tmpZR, 8);
+    if (reg_name == "tmpCY") return maat::ir::Reg(maat::ARM32::tmpCY, 8);
+    if (reg_name == "tmpOV") return maat::ir::Reg(maat::ARM32::tmpOV, 8);
+    if (reg_name == "shift_carry") return maat::ir::Reg(maat::ARM32::SC, 8);
+
     throw maat::runtime_exception(maat::Fmt()
             << "ARM32: Register translation from SLEIGH to MAAT missing for register "
             << reg_name