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Add latest snippy changes #4

Merged
merged 8 commits into from
Feb 13, 2024
Merged

Add latest snippy changes #4

merged 8 commits into from
Feb 13, 2024

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asi-sc
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@asi-sc asi-sc commented Feb 12, 2024

This PR contains changes that:

  • improve reproducibility with the same seed value
  • contain fixes for a non-stable test, typos, warnings
  • provide better diagnostic on invalid registers use and incorrect input configs
  • allow setting weights of JAL and JALR opcodes in the histogram

@asi-sc asi-sc requested a review from kv-sc February 12, 2024 13:36
@kv-sc kv-sc merged commit a5c713f into main Feb 13, 2024
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asi-sc pushed a commit to asi-sc/snippy that referenced this pull request Jan 10, 2025
Somewhat confusingly a `SCEVMulExpr` is a `SCEVNAryExpr`, so can have
> 2 operands. Previously, the vscale immediate matching did not check
the number of operands of the `SCEVMulExpr`, so would ignore any
operands after the first two.

This led to incorrect codegen (and results) for ArmSME in IREE
(https://github.com/iree-org/iree), which sometimes addresses things
that are a `vscale * vscale` multiple away. The test added with this
change shows an example reduced from IREE. The second write should
be offset from the first `16 * vscale * vscale` (* 4 bytes), however,
previously LSR dropped the second vscale and instead offset the write by
`syntacore#4, mul vl`, which is an offset of `16 * vscale` (* 4 bytes).

(cherry picked from commit 7fad04e94b7b594389111ae7eca0883ef18dc90b)
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6 participants