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Fix compilation warnings #147

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merged 1 commit into from
Jan 13, 2025
Merged

Fix compilation warnings #147

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7 changes: 3 additions & 4 deletions llvm/tools/llvm-snippy/include/snippy/Generator/RegisterPool.h
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Original file line number Diff line number Diff line change
Expand Up @@ -685,10 +685,9 @@ RegPool::getNAvailableRegisters(const Twine &Desc, const MCRegisterInfo &RI,
template <typename... IsReservedTys>
unsigned RegPoolWrapper::getNumAvailable(const MCRegisterClass &RegClass,
IsReservedTys &&...Args) const {
return std::count_if(
RegClass.begin(), RegClass.end(), [&Args..., this](auto Reg) {
return !isReserved(Reg, std::forward<IsReservedTys>(Args)...);
});
return std::count_if(RegClass.begin(), RegClass.end(), [&](auto Reg) {
return !isReserved(Reg, std::forward<IsReservedTys>(Args)...);
});
}

template <typename Pred, typename... IsReservedTys,
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5 changes: 3 additions & 2 deletions llvm/tools/llvm-snippy/lib/Generator/CFPermutation.cpp
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Expand Up @@ -146,8 +146,9 @@ findMaxDepthReachedImpl(CFPermBIIter Beg, CFPermBIIter End,
llvm::snippy::CFPermutationContext::CFPermutationContext(
MachineFunction &MF, GeneratorContext &GC, FunctionGenerator &FG,
ConsecutiveLoopInfo &CLI, const SimulatorContext &SimCtx)
: BlocksInfo(), CurrMF(MF), GC(GC), FG(FG), CLI(CLI), SimCtx(SimCtx),
BranchSettings(GC.getConfig().Branches) {
: BlocksInfo(), CurrMF(MF), GC(GC), FG(FG), CLI(CLI),
BranchSettings(GC.getConfig().Branches), SimCtx(SimCtx) {

auto &ProgCtx = GC.getProgramContext();

if (SimCtx.hasTrackingMode() &&
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5 changes: 1 addition & 4 deletions llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -938,9 +938,8 @@ class SnippyRISCVTarget final : public SnippyTarget {
return InstBuilder.addReg(SrcReg).addReg(SrcReg);
case RISCVMatInt::RegImm:
return InstBuilder.addReg(SrcReg).addImm(Inst.getImm());
default:
llvm_unreachable("Unsupported register type");
}
llvm_unreachable("Unsupported register type");
});
}

Expand Down Expand Up @@ -3214,7 +3213,6 @@ void SnippyRISCVTarget::rvvWriteValue(InstructionGenerationContext &IGC,
APInt Value, unsigned DstReg) const {
const auto &SimCtx = IGC.SimCtx;
auto &ProgCtx = IGC.ProgCtx;
auto &State = ProgCtx.getLLVMState();
// FIXME for V0 we can only use global variables for initialization
if (!InitVRegsFromMemory.getValue() && DstReg != RISCV::V0) {
rvvWriteValueUsingXReg(IGC, Value, DstReg);
Expand Down Expand Up @@ -3411,7 +3409,6 @@ void SnippyRISCVTarget::generateVSETVLI(InstructionGenerationContext &IGC,
auto &MBB = IGC.MBB;
auto &Ins = IGC.Ins;
auto &ProgCtx = IGC.ProgCtx;
auto &State = ProgCtx.getLLVMState();
// TODO 1: if VL is equal to VLMAX we can use X0 if DstReg is not zero
// TODO 2: if VL is not changed, and DST is zero, scratch VL can be zero
const auto &RI = ProgCtx.getLLVMState().getRegInfo();
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