Fix compilation warnings

syntacore · Jan 13, 2025 · 599c442 · 599c442
1 parent 43dbcd6
commit 599c442
Show file tree

Hide file tree

Showing 3 changed files with 7 additions and 10 deletions.
diff --git a/llvm/tools/llvm-snippy/include/snippy/Generator/RegisterPool.h b/llvm/tools/llvm-snippy/include/snippy/Generator/RegisterPool.h
@@ -685,10 +685,9 @@ RegPool::getNAvailableRegisters(const Twine &Desc, const MCRegisterInfo &RI,
 template <typename... IsReservedTys>
 unsigned RegPoolWrapper::getNumAvailable(const MCRegisterClass &RegClass,
                                          IsReservedTys &&...Args) const {
-  return std::count_if(
-      RegClass.begin(), RegClass.end(), [&Args..., this](auto Reg) {
-        return !isReserved(Reg, std::forward<IsReservedTys>(Args)...);
-      });
+  return std::count_if(RegClass.begin(), RegClass.end(), [&](auto Reg) {
+    return !isReserved(Reg, std::forward<IsReservedTys>(Args)...);
+  });
 }
 
 template <typename Pred, typename... IsReservedTys,

diff --git a/llvm/tools/llvm-snippy/lib/Generator/CFPermutation.cpp b/llvm/tools/llvm-snippy/lib/Generator/CFPermutation.cpp
@@ -146,8 +146,9 @@ findMaxDepthReachedImpl(CFPermBIIter Beg, CFPermBIIter End,
 llvm::snippy::CFPermutationContext::CFPermutationContext(
     MachineFunction &MF, GeneratorContext &GC, FunctionGenerator &FG,
     ConsecutiveLoopInfo &CLI, const SimulatorContext &SimCtx)
-    : BlocksInfo(), CurrMF(MF), GC(GC), FG(FG), CLI(CLI), SimCtx(SimCtx),
-      BranchSettings(GC.getConfig().Branches) {
+    : BlocksInfo(), CurrMF(MF), GC(GC), FG(FG), CLI(CLI),
+      BranchSettings(GC.getConfig().Branches), SimCtx(SimCtx) {
+
   auto &ProgCtx = GC.getProgramContext();
 
   if (SimCtx.hasTrackingMode() &&

diff --git a/llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp b/llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp
@@ -938,9 +938,8 @@ class SnippyRISCVTarget final : public SnippyTarget {
                         return InstBuilder.addReg(SrcReg).addReg(SrcReg);
                       case RISCVMatInt::RegImm:
                         return InstBuilder.addReg(SrcReg).addImm(Inst.getImm());
-                      default:
-                        llvm_unreachable("Unsupported register type");
                       }
+                      llvm_unreachable("Unsupported register type");
                     });
   }
 
@@ -3214,7 +3213,6 @@ void SnippyRISCVTarget::rvvWriteValue(InstructionGenerationContext &IGC,
                                       APInt Value, unsigned DstReg) const {
   const auto &SimCtx = IGC.SimCtx;
   auto &ProgCtx = IGC.ProgCtx;
-  auto &State = ProgCtx.getLLVMState();
   // FIXME for V0 we can only use global variables for initialization
   if (!InitVRegsFromMemory.getValue() && DstReg != RISCV::V0) {
     rvvWriteValueUsingXReg(IGC, Value, DstReg);
@@ -3411,7 +3409,6 @@ void SnippyRISCVTarget::generateVSETVLI(InstructionGenerationContext &IGC,
   auto &MBB = IGC.MBB;
   auto &Ins = IGC.Ins;
   auto &ProgCtx = IGC.ProgCtx;
-  auto &State = ProgCtx.getLLVMState();
   // TODO 1: if VL is equal to VLMAX we can use X0 if DstReg is not zero
   // TODO 2: if VL is not changed, and DST is zero, scratch VL can be zero
   const auto &RI = ProgCtx.getLLVMState().getRegInfo();