It's just a simple testbench generator to test the VHDL implementation of the project 051228-Prova finale (progetto di reti logiche) held at Politecnico di Milano.
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A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.
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ste7en/Project-Reti-Logiche-Testbench-Generator
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A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.
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