Stream vcs

[swamy-t]

I am creating the pull request for the develop branch just to check the mergeability. I think these changes will be pulled into a new branch.

[raghup17]

@swamy-t

The changes are in a new 'stream-vcs' branch. There are a couple of errors during Chisel compilation:

[error] /home/raghu/work/research/spatial/spatial-clean/spatial-lang/gen/SimpleTileLoadStore/chisel/Top.scala:227: value genericStreams is not a member of chisel3.Bundle{val enable: chisel3.core.Bool; val done: chisel3.core.Bool; val memStreams: fringe.AppStreams; val argIns: chisel3.core.Vec[chisel3.core.UInt]; val argOuts: chisel3.core.Vec[chisel3.util.DecoupledIO[chisel3.core.UInt]]; val stream_in_data: chisel3.core.UInt; val stream_in_startofpacket: chisel3.core.Bool; val stream_in_endofpacket: chisel3.core.Bool; val stream_in_empty: chisel3.core.UInt; val stream_in_valid: chisel3.core.Bool; val stream_out_ready: chisel3.core.Bool; val stream_in_ready: chisel3.core.Bool; val stream_out_data: chisel3.core.UInt; val stream_out_startofpacket: chisel3.core.Bool; val stream_out_endofpacket: chisel3.core.Bool; val stream_out_empty: chisel3.core.UInt; val stream_out_valid: chisel3.core.Bool; val led_stream_out_data: chisel3.core.UInt; val switch_stream_in_data: chisel3.core.UInt; val buffout_address: chisel3.core.UInt; val buffout_write: chisel3.core.UInt; val buffout_writedata: chisel3.core.UInt; val buffout_waitrequest: chisel3.core.UInt; val gpi1_streamin_readdata: chisel3.core.UInt; val gpo1_streamout_writedata: chisel3.core.UInt; val gpi2_streamin_readdata: chisel3.core.UInt; val gpo2_streamout_writedata: chisel3.core.UInt}
[error]       accel.io.genericStreams <> fringe.io.genericStreamsAccel
[error]                ^
[error] /home/raghu/work/research/spatial/spatial-clean/spatial-lang/gen/SimpleTileLoadStore/chisel/Top.scala:228: value genericStreams is not a member of chisel3.Bundle{val enable: chisel3.core.Bool; val done: chisel3.core.Bool; val memStreams: fringe.AppStreams; val argIns: chisel3.core.Vec[chisel3.core.UInt]; val argOuts: chisel3.core.Vec[chisel3.util.DecoupledIO[chisel3.core.UInt]]; val stream_in_data: chisel3.core.UInt; val stream_in_startofpacket: chisel3.core.Bool; val stream_in_endofpacket: chisel3.core.Bool; val stream_in_empty: chisel3.core.UInt; val stream_in_valid: chisel3.core.Bool; val stream_out_ready: chisel3.core.Bool; val stream_in_ready: chisel3.core.Bool; val stream_out_data: chisel3.core.UInt; val stream_out_startofpacket: chisel3.core.Bool; val stream_out_endofpacket: chisel3.core.Bool; val stream_out_empty: chisel3.core.UInt; val stream_out_valid: chisel3.core.Bool; val led_stream_out_data: chisel3.core.UInt; val switch_stream_in_data: chisel3.core.UInt; val buffout_address: chisel3.core.UInt; val buffout_write: chisel3.core.UInt; val buffout_writedata: chisel3.core.UInt; val buffout_waitrequest: chisel3.core.UInt; val gpi1_streamin_readdata: chisel3.core.UInt; val gpo1_streamout_writedata: chisel3.core.UInt; val gpi2_streamin_readdata: chisel3.core.UInt; val gpo2_streamout_writedata: chisel3.core.UInt}
[error]       fringe.io.genericStreamsAccel <> accel.io.genericStreams
[error]

Looks like your changes in argon were not merged. I would recommend creating a new argon branch, and add your changes there and push. You can then run the regression suite using bin/run_regression.sh to make sure nothing else is broken.