HPC interrupt firmware

examples/headsail-bsp/Cargo.toml

@@ -6,13 +6,16 @@ edition = "2021"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [features]
-hpc-rt = ["rt"]
+hpc-rt = ["hpc", "rt", "dep:riscv-peripheral", "dep:riscv-pac"]
 sysctrl-rt = [
+    "sysctrl",
     "rt",
     "riscv-rt/single-hart",
     "riscv/critical-section-single-hart",
 ]
 panic-uart = []
+hpc = []
+sysctrl = []
 
 # This is generated by the above options, don't use directly
 rt = ["dep:riscv-rt", "dep:riscv"]
@@ -21,6 +24,8 @@ rt = ["dep:riscv-rt", "dep:riscv"]
 ufmt = "0.2.0"
 riscv-rt = { version = "0.12.2", optional = true }
 riscv = { version = "0.11.1", optional = true }
+riscv-peripheral = { version = "0.1.0", optional = true }
+riscv-pac = { version = "0.1.1", optional = true }
 
 [[example]]
 name = "panic"

examples/headsail-bsp/src/hpc/interrupt.rs

@@ -0,0 +1,71 @@
+use crate::HartId;
+use riscv_pac::PriorityNumber;
+
+// HPC-SS specifies that priorities go up to 7
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Priority {
+    P0 = 0,
+    P1 = 1,
+    P2 = 2,
+    P3 = 3,
+    P4 = 4,
+    P5 = 5,
+    P6 = 6,
+    P7 = 7,
+}
+
+unsafe impl PriorityNumber for Priority {
+    const MAX_PRIORITY_NUMBER: u8 = 7;
+
+    #[inline]
+    fn number(self) -> u8 {
+        self as _
+    }
+
+    #[inline]
+    fn from_number(number: u8) -> Result<Self, u8> {
+        if number > Self::MAX_PRIORITY_NUMBER {
+            Err(number)
+        } else {
+            // SAFETY: valid priority number
+            Ok(unsafe { core::mem::transmute(number) })
+        }
+    }
+}
+
+riscv_peripheral::clint_codegen!(
+    base 0x60000,
+    freq 32_768,
+    mtimecmps [
+        mtimecmp0 = (HartId::H0, "`H0`"),
+        mtimecmp1 = (HartId::H1, "`H1`"),
+        mtimecmp2 = (HartId::H2, "`H2`"),
+        mtimecmp3 = (HartId::H3, "`H3`")
+    ],
+    msips [
+        msip0 = (HartId::H0, "`H0`"),
+        msip1 = (HartId::H1, "`H1`"),
+        msip2 = (HartId::H2, "`H2`"),
+        msip3 = (HartId::H3, "`H3`")
+    ],
+);
+
+// ???: ASIC developer beware
+//
+// Some addresses were tightened to save space for Headsail's PLIC. That means that the ASIC will be
+// different from the sim, and that this `riscv_peripheral` provided driver won't work as-is on
+// ASIC, while it works perfectly well with the sim.
+riscv_peripheral::plic_codegen!(
+    base 0x80000,
+    ctxs [
+        ctx0 = (HartId::H0, "`H0M`"),
+        ctx1 = (HartId::H0, "`H0S`"),
+        ctx2 = (HartId::H1, "`H1M`"),
+        ctx3 = (HartId::H1, "`H1S`"),
+        ctx4 = (HartId::H2, "`H2M`"),
+        ctx5 = (HartId::H2, "`H2S`"),
+        ctx6 = (HartId::H3, "`H3M`"),
+        ctx7 = (HartId::H3, "`H3S`")
+    ],
+);

examples/headsail-bsp/src/hpc/mod.rs

@@ -0,0 +1,35 @@
+//! Abstractions that only exist on HPC
+
+pub mod interrupt;
+pub use interrupt::*;
+
+use riscv_pac::HartIdNumber;
+
+/// HPC has 4 HARTs
+#[repr(u16)]
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum HartId {
+    H0 = 0,
+    H1 = 1,
+    H2 = 2,
+    H3 = 3,
+}
+
+unsafe impl HartIdNumber for HartId {
+    const MAX_HART_ID_NUMBER: u16 = 3;
+
+    #[inline]
+    fn number(self) -> u16 {
+        self as _
+    }
+
+    #[inline]
+    fn from_number(number: u16) -> Result<Self, u16> {
+        if number > Self::MAX_HART_ID_NUMBER {
+            Err(number)
+        } else {
+            // SAFETY: valid context number
+            Ok(unsafe { core::mem::transmute(number) })
+        }
+    }
+}

examples/headsail-bsp/src/lib.rs

@@ -4,10 +4,15 @@
 pub mod sprintln;
 pub mod uart;
 
-#[cfg(any(feature = "rt"))]
+#[cfg(feature = "hpc")]
+pub use hpc::*;
+pub use riscv;
+#[cfg(feature = "rt")]
 pub use riscv_rt as rt;
 pub use ufmt;
 
+#[cfg(feature = "hpc")]
+mod hpc;
 mod mmap;
 #[cfg(any(feature = "panic-uart"))]
 mod ufmt_panic;

vp/devel/hpc.repl

@@ -22,7 +22,7 @@ sdram: Memory.MappedMemory @ sysbus 0x10000000
     size: 0x60000000
 
 /*
- * CLINT <> [^1]
+ * CLINT [^1]
  *
  * [IP](https://gitlab.tuni.fi/soc-hub/common/hw/cva6/-/tree/master/corev_apu/clint)
  * [Specification](https://github.com/pulp-platform/clint) (unconfirmed)
@@ -33,7 +33,7 @@ clint: IRQControllers.CoreLevelInterruptor  @ sysbus 0x60000
     [4, 5] -> cpu_hpc2@[3, 7] // msoft, mtimer
     [6, 7] -> cpu_hpc3@[3, 7] // msoft, mtimer
     numberOfTargets: 4
-    frequency: 100000 // we guess board reference frequency
+    frequency: 32768 // we guess the usual RTC freq. of 32.768 kHz
 
 /*
  * PLIC [^1]