xtensa RzIL #4712
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xtensa RzIL #4712
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XVilka
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| SETG(REGN(0), SHIFTL0(IREG(1), VARL("sa")))); | ||
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| // TODO: see Divide and Square Root Sequences on page 110. |
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I'm planning to do this in another new PR, and the instructions are so strange that I'm not sure it's necessary to implement them.
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It depends if these instructions are used in the real code or not. Yep, it's okay to do in a subsequent PR.
| return NOP(); | ||
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| // TODO: datatlb |
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I think these todos aren't needed. There is no point of uplifting barrier instructions to RzIL, I think.
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities. - **Instruction Set Additions**: - **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8 - **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa - **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez - **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src - **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex - **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw - **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s - **Testing and Patches**: - Implement asm tests for all - **Miscellaneous Improvements**: - Update Capstone and fix ARM architecture support for building. This commit consolidates various enhancements, bug fixes, and testing for Xtensa architecture within rzil framework.
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XVilka
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xtensa: add rzil support
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