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[AArch64/ARM64] Update to Capstone v6/auto-sync #3963

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[AArch64/ARM64] Update to Capstone v6/auto-sync #3963

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da8ab70
[AArch64 CS v6 BEGIN] Change subproject config to use cs-auto-sync-aa…
Rot127 Aug 24, 2023
d0c6569
Replace ARM64 with version sensitive macros.
Rot127 Aug 26, 2023
c822f15
Exclude alias if CS version >= 6
Rot127 Aug 26, 2023
434c22e
Update access to writeback member
Rot127 Aug 26, 2023
db63fb9
Exclude instr alias from inclusion
Rot127 Aug 26, 2023
0383120
Update memory operand printing to json.
Rot127 Aug 26, 2023
c04f3a2
Enable real instr. detail only for AArch64
Rot127 Aug 26, 2023
9c3ecc6
Set correct arch name in meson.build for CS
Rot127 Aug 26, 2023
28cd385
Fix U/SBFM instructions and their alias.
Rot127 Aug 27, 2023
9f25f83
Mark parameters with RZ_OUt/BORROW
Rot127 Aug 27, 2023
d53ad83
Optimize register extension to skip some, if the width already matches.
Rot127 Aug 27, 2023
e639f1b
Adapt width and lsb of U/SBFM alias instructions (ImmR and ImmS are f…
Rot127 Aug 28, 2023
6a7888a
Fix tests correct semantic buy bad syntax
Rot127 Aug 28, 2023
144fb48
Pass alias MOV instructions to mov()
Rot127 Aug 28, 2023
c14f1a8
Handle CSET and CSETM alias
Rot127 Aug 28, 2023
af32784
Fix lsl, lsr and asr by handling them as alias.
Rot127 Aug 28, 2023
d9a8b4b
Fix mov alias.
Rot127 Aug 29, 2023
521bb08
Handle TST alias
Rot127 Aug 29, 2023
e3631f2
Fix CNEG, CINV alias
Rot127 Aug 29, 2023
cef14b1
Fix bfi and bfxil alias.
Rot127 Aug 29, 2023
9d00c68
Fix sign extensions.
Rot127 Aug 29, 2023
22beb9d
Fix compare instructions.
Rot127 Aug 29, 2023
90a0a9c
Fix NEG, NGC, NGCS, NEGS, MVN
Rot127 Aug 29, 2023
4bd80e8
Fix CINC
Rot127 Aug 29, 2023
4c9c49b
Fix multiply instructions.
Rot127 Aug 29, 2023
bd7273d
Fix ROR
Rot127 Aug 29, 2023
8af481b
Run clang-format
Rot127 Aug 29, 2023
29cf620
Handle CMP for ESIL
Rot127 Aug 30, 2023
79f019b
Handle new position of memory disponents of post index operands.
Rot127 Aug 30, 2023
3d41ea1
Fix post-index operations.
Rot127 Aug 30, 2023
ed232f1
Add missing writeback checks for Post and preindex
Rot127 Aug 30, 2023
3c4c91a
Handle UBFM and SBFM alias
Rot127 Aug 30, 2023
a853a50
Handl BFM alias
Rot127 Aug 30, 2023
11f8ede
Handle CMP, CSET and CINC alias
Rot127 Aug 30, 2023
6156869
Update meson file of for cs-aarch64 branch
Rot127 Oct 11, 2023
c242cb6
Fix asm tests. Use reg alias now.
Rot127 Oct 11, 2023
c6c78cd
Fix condition confusion and incorrect operand usage.
Rot127 Oct 12, 2023
2bd5207
Fix plf test.
Rot127 Oct 13, 2023
1035edd
Run clang-format
Rot127 Oct 13, 2023
daa9d11
Use register alias in tests
Rot127 Oct 13, 2023
761d845
Add support for fp and lr reg alias assembly.
Rot127 Oct 14, 2023
07783a8
Use reg alias in test
Rot127 Oct 14, 2023
d1e6ffa
Rename cond tranlate functions r2 -> rz
Rot127 Oct 14, 2023
4258742
Fix condition check which assume 0 == invalid.
Rot127 Oct 14, 2023
18a48e1
Fix issues intruduced by rebase
Rot127 Nov 6, 2023
94a15ef
Set CS commit to current next branch.
Rot127 Nov 16, 2023
d109f5c
Rename ARM64 -> AArch64
Rot127 Nov 17, 2023
beffb6e
Add missing source file to meson.build
Rot127 Nov 17, 2023
51e31fb
Remove DisassemblerExtension.c file for CS v5
Rot127 Nov 17, 2023
dda2ce5
Update to newest capstone next branch
Rot127 Nov 27, 2023
9fa1125
Bump up CS version
Rot127 Nov 30, 2023
2070f2b
REVERT ME: Get Capstone v4/v5 via git clone until new tars are released.
Rot127 Nov 27, 2023
2daf3ea
Wrap setting of CS_DETAIL_REAL into CS version check
Rot127 Nov 30, 2023
411670f
Add maybe-unitialized to Capstone C args.
Rot127 Nov 30, 2023
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31 changes: 20 additions & 11 deletions librz/analysis/arch/arm/arm_accessors64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,21 +9,30 @@

#include <capstone/capstone.h>

#define IMM64(x) (ut64)(insn->detail->arm64.operands[x].imm)
#define INSOP64(x) insn->detail->arm64.operands[x]
#define IMM64(x) (ut64)(insn->detail->CS_aarch64().operands[x].imm)
#define INSOP64(x) insn->detail->CS_aarch64().operands[x]

#define REGID64(x) insn->detail->arm64.operands[x].reg
#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
#define REGID64(x) insn->detail->CS_aarch64().operands[x].reg
#define REGBASE64(x) insn->detail->CS_aarch64().operands[x].mem.base
// s/index/base|reg/
#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID)
#define MEMDISP64(x) (ut64) insn->detail->arm64.operands[x].mem.disp
#define ISIMM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_IMM)
#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)
#define HASMEMINDEX64(x) (insn->detail->CS_aarch64().operands[x].mem.index != CS_AARCH64(_REG_INVALID))
#define MEMDISP64(x) (ut64) insn->detail->CS_aarch64().operands[x].mem.disp
#define ISIMM64(x) (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_IMM))
#define ISREG64(x) (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_REG))
#define ISMEM64(x) (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_MEM))

#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
#define OPCOUNT64() insn->detail->arm64.op_count
#define LSHIFT2_64(x) insn->detail->CS_aarch64().operands[x].shift.value
#define OPCOUNT64() insn->detail->CS_aarch64().op_count

#if CS_NEXT_VERSION < 6
#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
#else
#define ISWRITEBACK64() (insn->detail->writeback == true)
#endif
#if CS_NEXT_VERSION < 6
#define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
#define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64())))
#else
#define ISPREINDEX64() (!insn->detail->CS_aarch64().post_index && ISWRITEBACK64())
#define ISPOSTINDEX64() (insn->detail->CS_aarch64().post_index && ISWRITEBACK64())
#endif
2 changes: 1 addition & 1 deletion librz/analysis/arch/arm/arm_cs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode
#else
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
#endif
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type);

RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);
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