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Remove no longer existing alias and some name changes.
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@Rot127
Rot127 committed Aug 25, 2023
1 parent 7961265 commit af63f9e
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Showing 4 changed files with 112 additions and 374 deletions.
142 changes: 71 additions & 71 deletions librz/analysis/arch/arm/arm_esil64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -363,10 +363,10 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
rz_strbuf_setf(&op->esil, "%s,%s,*,%s,-,%s,=",
REG64(2), REG64(1), REG64(3), REG64(0));
break;
case AArch64_INS_MNEG:
rz_strbuf_setf(&op->esil, "%s,%s,*,0,-,%s,=",
REG64(2), REG64(1), REG64(0));
break;
// case AArch64_INS_MNEG:
// rz_strbuf_setf(&op->esil, "%s,%s,*,0,-,%s,=",
// REG64(2), REG64(1), REG64(0));
// break;
case AArch64_INS_ADD:
case AArch64_INS_ADC: // Add with carry.
// case AArch64_INS_ADCS: // Add with carry.
Expand Down Expand Up @@ -445,7 +445,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
case AArch64_INS_ROR:
OPCALL(">>>");
break;
case AArch64_INS_NOP:
case AArch64_INS_HINT:
rz_strbuf_setf(&op->esil, ",");
break;
case AArch64_INS_FDIV:
Expand Down Expand Up @@ -733,9 +733,9 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
case AArch64_INS_FCMP:
case AArch64_INS_CCMP:
case AArch64_INS_CCMN:
case AArch64_INS_TST: // cmp w8, 0xd
case AArch64_INS_CMP: // cmp w8, 0xd
case AArch64_INS_CMN: // cmp w8, 0xd
// case AArch64_INS_TST: // cmp w8, 0xd
// case AArch64_INS_CMP: // cmp w8, 0xd
// case AArch64_INS_CMN: // cmp w8, 0xd
{
// update esil, cpu flags
int bits = aarch64_reg_width(REGID64(0));
Expand All @@ -753,18 +753,18 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
rz_strbuf_appendf(&op->esil, "%s,}{,%s,},%s,=", REG64(1), REG64(2), REG64(0));
postfix = "";
break;
case AArch64_INS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0
rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0));
postfix = "";
break;
case AArch64_INS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn
rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0));
postfix = "";
break;
case AArch64_INS_CSINC: // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1)
rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0));
postfix = "";
break;
// case AArch64_INS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0
// rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0));
// postfix = "";
// break;
// case AArch64_INS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn
// rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0));
// postfix = "";
// break;
// case AArch64_INS_CSINC: // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1)
// rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0));
// postfix = "";
// break;
case AArch64_INS_STXRB:
case AArch64_INS_STXRH:
case AArch64_INS_STXR: {
Expand Down Expand Up @@ -1000,7 +1000,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
rz_strbuf_setf(&op->esil, "0xffffffff00000000,0x20,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x20,0xffffffff00000000,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,%2$s,=",
REG64(1), REG64(0));
break;
case AArch64_INS_MVN:
// case AArch64_INS_MVN:
case AArch64_INS_MOVN:
if (ISREG64(1)) {
rz_strbuf_setf(&op->esil, "%d,%s,-1,^,<<,%s,=", LSHIFT2_64(1), REG64(1), REG64(0));
Expand Down Expand Up @@ -1090,56 +1090,56 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
case AArch64_INS_ERET:
rz_strbuf_setf(&op->esil, "lr,pc,=");
break;
case AArch64_INS_BFI: // bfi w8, w8, 2, 1
case AArch64_INS_BFXIL: {
if (OPCOUNT64() >= 3 && ISIMM64(3) && IMM64(3) > 0) {
ut64 mask = rz_num_bitmask((ut8)IMM64(3));
ut64 shift = IMM64(2);
ut64 notmask = ~(mask << shift);
// notmask,dst,&,lsb,mask,src,&,<<,|,dst,=
rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,&,%" PFMT64u ",%" PFMT64u ",%s,&,<<,|,%s,=",
notmask, REG64(0), shift, mask, REG64(1), REG64(0));
}
break;
}
case AArch64_INS_SBFIZ:
if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=",
IMM64(2), IMM64(3), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
}
break;
case AArch64_INS_UBFIZ:
if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=",
IMM64(2), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
}
break;
case AArch64_INS_SBFX:
if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=",
IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
}
break;
case AArch64_INS_UBFX:
if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=",
IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
}
break;
case AArch64_INS_NEG:
#if CS_API_MAJOR > 3
case AArch64_INS_NEGS:
#endif
if (LSHIFT2_64(1)) {
SHIFTED_REG64_APPEND(&op->esil, 1);
} else {
rz_strbuf_appendf(&op->esil, "%s", REG64(1));
}
rz_strbuf_appendf(&op->esil, ",0,-,%s,=", REG64(0));
break;
case AArch64_INS_SVC:
rz_strbuf_setf(&op->esil, "%" PFMT64u ",$", IMM64(0));
break;
// case AArch64_INS_BFI: // bfi w8, w8, 2, 1
// case AArch64_INS_BFXIL: {
// if (OPCOUNT64() >= 3 && ISIMM64(3) && IMM64(3) > 0) {
// ut64 mask = rz_num_bitmask((ut8)IMM64(3));
// ut64 shift = IMM64(2);
// ut64 notmask = ~(mask << shift);
// // notmask,dst,&,lsb,mask,src,&,<<,|,dst,=
// rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,&,%" PFMT64u ",%" PFMT64u ",%s,&,<<,|,%s,=",
// notmask, REG64(0), shift, mask, REG64(1), REG64(0));
// }
// break;
// }
// case AArch64_INS_SBFIZ:
// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=",
// IMM64(2), IMM64(3), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
// }
// break;
// case AArch64_INS_UBFIZ:
// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=",
// IMM64(2), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
// }
// break;
// case AArch64_INS_SBFX:
// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=",
// IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
// }
// break;
// case AArch64_INS_UBFX:
// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=",
// IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
// }
// break;
// case AArch64_INS_NEG:
// #if CS_API_MAJOR > 3
// case AArch64_INS_NEGS:
// #endif
// if (LSHIFT2_64(1)) {
// SHIFTED_REG64_APPEND(&op->esil, 1);
// } else {
// rz_strbuf_appendf(&op->esil, "%s", REG64(1));
// }
// rz_strbuf_appendf(&op->esil, ",0,-,%s,=", REG64(0));
// break;
// case AArch64_INS_SVC:
// rz_strbuf_setf(&op->esil, "%" PFMT64u ",$", IMM64(0));
// break;
}

rz_strbuf_append(&op->esil, postfix);
Expand Down
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