Replace ARM64 with version sensitive macros.

rizinorg · Aug 26, 2023 · 3ef7b49 · 3ef7b49
1 parent ea233f6
commit 3ef7b49
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Showing 5 changed files with 1,448 additions and 1,448 deletions.
diff --git a/librz/analysis/arch/arm/arm_accessors64.h b/librz/analysis/arch/arm/arm_accessors64.h
@@ -9,25 +9,25 @@
 
 #include <capstone/capstone.h>
 
-#define IMM64(x)   (ut64)(insn->detail->arm64.operands[x].imm)
-#define INSOP64(x) insn->detail->arm64.operands[x]
+#define IMM64(x)   (ut64)(insn->detail->CS_aarch64().operands[x].imm)
+#define INSOP64(x) insn->detail->CS_aarch64().operands[x]
 
-#define REGID64(x)   insn->detail->arm64.operands[x].reg
-#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
+#define REGID64(x)   insn->detail->CS_aarch64().operands[x].reg
+#define REGBASE64(x) insn->detail->CS_aarch64().operands[x].mem.base
 // s/index/base|reg/
-#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID)
-#define MEMDISP64(x)     (ut64) insn->detail->arm64.operands[x].mem.disp
-#define ISIMM64(x)       (insn->detail->arm64.operands[x].type == ARM64_OP_IMM)
-#define ISREG64(x)       (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
-#define ISMEM64(x)       (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)
+#define HASMEMINDEX64(x) (insn->detail->CS_aarch64().operands[x].mem.index != CS_AARCH64(_REG_INVALID))
+#define MEMDISP64(x)     (ut64) insn->detail->CS_aarch64().operands[x].mem.disp
+#define ISIMM64(x)       (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_IMM))
+#define ISREG64(x)       (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_REG))
+#define ISMEM64(x)       (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_MEM))
 
 #if CS_API_MAJOR > 3
-#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
+#define LSHIFT2_64(x) insn->detail->CS_aarch64().operands[x].shift.value
 #else
 #define LSHIFT2_64(x) 0
 #endif
-#define OPCOUNT64() insn->detail->arm64.op_count
+#define OPCOUNT64() insn->detail->CS_aarch64().op_count
 
-#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
+#define ISWRITEBACK64() (insn->detail->CS_aarch64().writeback == true)
 #define ISPREINDEX64()  (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
 #define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64())))
diff --git a/librz/analysis/arch/arm/arm_cs.h b/librz/analysis/arch/arm/arm_cs.h
@@ -13,7 +13,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
 RZ_IPI bool rz_arm_cs_is_group_member(const cs_insn *insn, arm_insn_group feature);
 
 RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCodes cond_type);
-RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);
+RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type);
 
 RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
 RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);