xtensa: add rzil support

- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
  - **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
  - **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
  - **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
  - **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
  - **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
  - **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
  - **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s

- **Testing and Patches**:
  - Implement asm tests for all

- **Miscellaneous Improvements**:
  - Update Capstone and fix ARM architecture support for building.

This commit consolidates various enhancements, bug fixes, and testing for Xtensa architecture within rzil framework.

librz/arch/isa/arm/arm_il32.c

@@ -3623,12 +3623,12 @@ RZ_IPI bool rz_arm_cs_is_float_insn(const cs_insn *insn) {
 		switch (group_it) {
 		default:
 			break;
-		case ARM_FEATURE_HasNEON:
-		case ARM_FEATURE_HasVFP2:
-		case ARM_FEATURE_HasVFP3:
-		case ARM_FEATURE_HasVFP4:
-		case ARM_FEATURE_HasDPVFP:
-		case ARM_FEATURE_HasMVEFloat:
+		case ARM_FEATURE_HASNEON:
+		case ARM_FEATURE_HASVFP2:
+		case ARM_FEATURE_HASVFP3:
+		case ARM_FEATURE_HASVFP4:
+		case ARM_FEATURE_HASDPVFP:
+		case ARM_FEATURE_HASMVEFLOAT:
 			return true;
 		}
 		group_it = insn->detail->groups[++i];
@@ -3653,7 +3653,7 @@ static RzILOpEffect *try_as_int_cvt(cs_insn *insn, bool is_thumb, bool *success)
 	ut32 fl_sz = rz_float_get_format_info(is_f2i ? from_fmt : to_fmt, RZ_FLOAT_INFO_TOTAL_LEN);
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif
@@ -3890,7 +3890,7 @@ static RzILOpEffect *vadd(cs_insn *insn, bool is_thumb) {
 	bool is_float_vec = fmt == RZ_FLOAT_UNK ? false : true;
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif
@@ -3941,7 +3941,7 @@ static RzILOpEffect *vsub(cs_insn *insn, bool is_thumb) {
 	bool is_float_vec = fmt == RZ_FLOAT_UNK ? false : true;
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif
@@ -3990,7 +3990,7 @@ static RzILOpEffect *vmul(cs_insn *insn, bool is_thumb) {
 	RzFloatFormat fmt = dt2fmt(dt);
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif

librz/arch/isa/xtensa/xtensa.h

@@ -31,6 +31,7 @@ bool xtensa_open(XtensaContext *ctx, const char *cpu, bool big_endian);
 bool xtensa_disassemble(XtensaContext *self, const ut8 *buf, int len, ut64 addr);
 void xtensa_disassemble_fini(XtensaContext *self);
 void xtensa_analyze_op_esil(XtensaContext *ctx, RzAnalysisOp *op);
+void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op);
 
 static inline cs_xtensa_op_mem *xtensa_op_mem(cs_insn *insn, unsigned int index) {
 	cs_xtensa_op *op = &insn->detail->xtensa.operands[index];
@@ -56,12 +57,13 @@ static inline int32_t xtensa_op_l32r(cs_insn *insn, unsigned int index) {
 	return op->imm;
 }
 
-#define XOP(I)    (ctx->insn->detail->xtensa.operands + I)
-#define MEM(I)    xtensa_op_mem(ctx->insn, I)
-#define REGI(I)   xtensa_op_reg(ctx->insn, I)
-#define REGN(I)   cs_reg_name(ctx->handle, (xtensa_op_reg(ctx->insn, I)))
-#define IMM(I)    xtensa_op_imm(ctx->insn, I)
-#define L32R(I)   xtensa_op_l32r(ctx->insn, I)
-#define INSN_SIZE (ctx->insn->size)
+#define XOP(I)     (ctx->insn->detail->xtensa.operands + I)
+#define MEM(I)     xtensa_op_mem(ctx->insn, I)
+#define REGI(I)    xtensa_op_reg(ctx->insn, I)
+#define REGNAME(I) cs_reg_name(ctx->handle, (I))
+#define REGN(I)    REGNAME(REGI((I)))
+#define IMM(I)     xtensa_op_imm(ctx->insn, I)
+#define L32R(I)    xtensa_op_l32r(ctx->insn, I)
+#define INSN_SIZE  (ctx->insn->size)
 
 #endif // RZ_XTENSA_H