Bump Capstone to newest next (#4758)

* Fix check for rfe, operand is now an memory operand. * Use ARM features upper case identifiers. * Bump Capstone to newest next. * Fix trivial tests
rizinorg · Dec 18, 2024 · 21fda95 · 21fda95
1 parent c0e58b1
commit 21fda95
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Showing 6 changed files with 26 additions and 26 deletions.
diff --git a/librz/arch/isa/arm/arm_il32.c b/librz/arch/isa/arm/arm_il32.c
@@ -1947,10 +1947,10 @@ static RzILOpEffect *revsh(cs_insn *insn, bool is_thumb) {
  * ARM: rfeda, rfedb, rfaia, rfeib
  */
 static RzILOpEffect *rfe(cs_insn *insn, bool is_thumb) {
-	if (!ISREG(0)) {
+	if (!ISMEM(0)) {
 		return NULL;
 	}
-	RzILOpBitVector *base = REG(0);
+	RzILOpBitVector *base = MEMBASE(0);
 	if (!base) {
 		return NULL;
 	}
@@ -3623,12 +3623,12 @@ RZ_IPI bool rz_arm_cs_is_float_insn(const cs_insn *insn) {
 		switch (group_it) {
 		default:
 			break;
-		case ARM_FEATURE_HasNEON:
-		case ARM_FEATURE_HasVFP2:
-		case ARM_FEATURE_HasVFP3:
-		case ARM_FEATURE_HasVFP4:
-		case ARM_FEATURE_HasDPVFP:
-		case ARM_FEATURE_HasMVEFloat:
+		case ARM_FEATURE_HASNEON:
+		case ARM_FEATURE_HASVFP2:
+		case ARM_FEATURE_HASVFP3:
+		case ARM_FEATURE_HASVFP4:
+		case ARM_FEATURE_HASDPVFP:
+		case ARM_FEATURE_HASMVEFLOAT:
 			return true;
 		}
 		group_it = insn->detail->groups[++i];
@@ -3653,7 +3653,7 @@ static RzILOpEffect *try_as_int_cvt(cs_insn *insn, bool is_thumb, bool *success)
 	ut32 fl_sz = rz_float_get_format_info(is_f2i ? from_fmt : to_fmt, RZ_FLOAT_INFO_TOTAL_LEN);
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif
@@ -3890,7 +3890,7 @@ static RzILOpEffect *vadd(cs_insn *insn, bool is_thumb) {
 	bool is_float_vec = fmt == RZ_FLOAT_UNK ? false : true;
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif
@@ -3941,7 +3941,7 @@ static RzILOpEffect *vsub(cs_insn *insn, bool is_thumb) {
 	bool is_float_vec = fmt == RZ_FLOAT_UNK ? false : true;
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif
@@ -3990,7 +3990,7 @@ static RzILOpEffect *vmul(cs_insn *insn, bool is_thumb) {
 	RzFloatFormat fmt = dt2fmt(dt);
 
 #if CS_NEXT_VERSION >= 6
-	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) {
+	if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HASNEON)) {
 #else
 	if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) {
 #endif

diff --git a/librz/arch/p/analysis/analysis_arm_cs.c b/librz/arch/p/analysis/analysis_arm_cs.c
@@ -1292,20 +1292,20 @@ static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, b
 
 	/* grab family */
 #if CS_NEXT_VERSION >= 6
-	if (cs_insn_group(handle, insn, ARM_FEATURE_HasAES)) {
+	if (cs_insn_group(handle, insn, ARM_FEATURE_HASAES)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
-	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HasCRC)) {
+	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HASCRC)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
 	} else if (cs_insn_group(handle, insn, ARM_GRP_PRIVILEGE)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
-	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HasVirtualization)) {
+	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HASVIRTUALIZATION)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_VIRT;
-	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HasNEON)) {
+	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HASNEON)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_MMX;
-	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HasFPARMv8)) {
+	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HASFPARMV8)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
-	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HasDSP) &&
-		cs_insn_group(handle, insn, ARM_FEATURE_HasDSP)) {
+	} else if (cs_insn_group(handle, insn, ARM_FEATURE_HASDSP) &&
+		cs_insn_group(handle, insn, ARM_FEATURE_HASDSP)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_MMX;
 	} else {
 		op->family = RZ_ANALYSIS_OP_FAMILY_CPU;

diff --git a/librz/arch/p/asm/asm_arm_cs.c b/librz/arch/p/asm/asm_arm_cs.c
@@ -41,9 +41,9 @@ static bool check_features(RzAsm *a, cs_insn *insn) {
 		int id = insn->detail->groups[i];
 		switch (id) {
 #if CS_NEXT_VERSION >= 6
-		case ARM_FEATURE_IsARM:
-		case ARM_FEATURE_IsThumb:
-		case ARM_FEATURE_IsThumb2:
+		case ARM_FEATURE_ISARM:
+		case ARM_FEATURE_ISTHUMB:
+		case ARM_FEATURE_ISTHUMB2:
 #else
 		case ARM_GRP_ARM:
 		case ARM_GRP_THUMB:

diff --git a/subprojects/capstone-next.wrap b/subprojects/capstone-next.wrap
@@ -1,6 +1,6 @@
 [wrap-git]
 url = https://github.com/capstone-engine/capstone.git
-revision = 1ecfb5b04235539e0d94cc67b8984347be2f6a73
+revision = 9907b22d33693f3beb4b8b7ba261fbdd219afee3
 directory = capstone-next
 patch_directory = capstone-next
 depth = 1
diff --git a/test/db/analysis/arm b/test/db/analysis/arm
@@ -912,7 +912,7 @@ pseudo: push (r3, lr)
 mnemonic: push
 mask: ffffffff
 prefix: 0
-id: 438
+id: 440
 bytes: 08402de9
 refptr: 0
 size: 4
@@ -935,7 +935,7 @@ mnemonic: add
 description: add two values
 mask: ffff
 prefix: 0
-id: 31
+id: 33
 bytes: 00af
 refptr: 0
 size: 2

diff --git a/test/db/analysis/ppc b/test/db/analysis/ppc
@@ -716,7 +716,7 @@ EXPECT=<<EOF
     },
     "sign": false,
     "prefix": 0,
-    "id": 942,
+    "id": 1004,
     "opex": {
       "operands": [
         {