[ACT] Add support for CMO

coverage/cmo/cbom.cgf

@@ -0,0 +1,37 @@
+# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
+
+cbo.clean:
+    config:
+      - check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
+    mnemonics:
+      cbo.clean: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      <<: [*base_rs1val_unsgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+
+cbo.flush:
+    config:
+      - check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
+    mnemonics:
+      cbo.flush: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      <<: [*base_rs1val_unsgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+
+cbo.inval:
+    config:
+      - check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
+    mnemonics:
+      cbo.inval: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      <<: [*base_rs1val_unsgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]

coverage/cmo/cbop.cgf

@@ -0,0 +1,37 @@
+# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
+
+prefetch.i:
+    config:
+      - check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
+    mnemonics:
+      prefetch.i: 0
+    rs1:
+      <<: *all_regs
+    val_comb:
+      <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]
+
+prefetch.r:
+    config:
+      - check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
+    mnemonics:
+      prefetch.r: 0
+    rs1:
+      <<: *all_regs
+    val_comb:
+      <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]
+
+prefetch.w:
+    config:
+      - check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
+    mnemonics:
+      prefetch.w: 0
+    rs1:
+      <<: *all_regs
+    val_comb:
+      <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]

coverage/cmo/rvi_cmo.cgf → coverage/cmo/cboz.cgf

@@ -1,14 +1,14 @@
 # For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
 
-cbozero:
+cbo.zero:
     config:
       - check ISA:=regex(.*I.*Zicboz.*Zicsr.*)
-    opcode:
+    mnemonics:
       cbo.zero: 0
     rs1:
       <<: *all_regs_mx0
     val_comb:
       abstract_comb:
         'walking_ones("rs1_val", 12, False)': 0
         'walking_zeros("rs1_val", 12, False)': 0
-        'uniform_random(10, 100, ["rs1_val"], [12])': 0
+        'uniform_random(20, 100, ["rs1_val"], [12])': 0

coverage/dataset.cgf

@@ -180,7 +180,7 @@ datasets:
     x13: 0
     x14: 0
     x15: 0
-  
+
   all_regs_mx2: &all_regs_mx2
     x1: 0
     x3: 0
@@ -295,7 +295,7 @@ datasets:
   r0fmt_op_comb: &r0fmt_op_comb
     'rs1 == 0': 0
     'rs1 != 0': 0
-  
+
   base_rs1val_sgn: &base_rs1val_sgn
     'rs1_val == (-2**(xlen-1))': 0
     'rs1_val == 0': 0
@@ -307,7 +307,7 @@ datasets:
     'rs1_val == 0 and rs2_val == 0': 0
     'rs1_val == (2**(xlen-1)-1) and rs2_val == 0': 0
     'rs1_val == 1 and rs2_val == 0': 0
-  
+
   base_rs2val_sgn: &base_rs2val_sgn
     'rs2_val == (-2**(xlen-1))': 0
     'rs2_val == 0': 0
@@ -320,12 +320,11 @@ datasets:
     'rs3_val == (2**(xlen-1)-1)': 0
     'rs3_val == 1': 0
 
-
   base_rs1val_unsgn: &base_rs1val_unsgn
     'rs1_val == 0': 0
     'rs1_val == (2**(xlen)-1)': 0
     'rs1_val == 1': 0
-  
+
   base_rs2val_unsgn: &base_rs2val_unsgn
     'rs2_val == 0': 0
     'rs2_val == (2**(xlen)-1)': 0
@@ -346,7 +345,7 @@ datasets:
 
   div_corner_case: &div_corner_case
     'rs1_val == -(2**(xlen-1)) and rs2_val == -0x01': 0
-  
+
   rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn
     'rs1_val > 0 and rs2_val > 0': 0
     'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0
@@ -364,12 +363,23 @@ datasets:
     'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0
     'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0
 
+  zicbop_ifmt_val_comb_unsgn: &zicbop_ifmt_val_comb_unsgn
+    'rs1_val == imm_val and rs1_val == 0': 0
+    'rs1_val < imm_val and rs1_val != 0': 0
+    'rs1_val > imm_val and imm_val == 0': 0
+
   ifmt_base_immval_sgn: &ifmt_base_immval_sgn
     'imm_val == (-2**(12-1))': 0
     'imm_val == 0': 0
     'imm_val == (2**(12-1)-1)': 0
     'imm_val == 1': 0
 
+  ifmt_base_immval11_5_sgn: &ifmt_base_immval11_5_sgn
+    'imm_val == (-2**(7-1)) << 5': 0
+    'imm_val == 0': 0
+    'imm_val == (2**(7-1)-1) << 5': 0
+    'imm_val == 1<<5': 0
+
   ifmt_base_immval_sgn_len: &ifmt_base_immval_sgn_len
     'imm_val == (-2**(ceil(log(xlen,2))-1))': 0
     'imm_val == 0': 0
@@ -435,7 +445,7 @@ datasets:
     'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
     'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0
     'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
-  
+
   bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn
     'rs1_val > 0 and rs2_val > 0': 0
     'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0
@@ -480,12 +490,17 @@ datasets:
     'walking_ones("imm_val", 5, False)': 0
     'walking_zeros("imm_val", 5, False)': 0
     'alternate("imm_val", 5, False)': 0
-
+
+  ifmt_immval_walking_11_5: &ifmt_immval_walking_11_5
+    'walking_ones("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
+    'walking_zeros("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
+    'alternate("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
+
   rs1val_walking_unsgn: &rs1val_walking_unsgn
     'walking_ones("rs1_val", xlen,False)': 0
     'walking_zeros("rs1_val", xlen,False)': 0
     'alternate("rs1_val",xlen,False)': 0
-  
+
   rs2val_walking_unsgn: &rs2val_walking_unsgn
     'walking_ones("rs2_val", xlen,False)': 0
     'walking_zeros("rs2_val", xlen,False)': 0
@@ -499,7 +514,7 @@ datasets:
     'walking_ones("imm_val", 6)': 0
     'walking_zeros("imm_val", 6)': 0
     'alternate("imm_val",6)': 0
-  
+
   ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn
     'walking_ones("imm_val", 12,False)': 0
     'walking_zeros("imm_val", 12,False)': 0

riscv-ctg/CHANGELOG.md

@@ -2,11 +2,13 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-
 Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch.
 Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
 versioned header while the `WIP-DEV` is left empty
 
+## [WIP-DEV]
+- Added support for zicboz extexnsion
+
 ## [0.12.2] - 2024-03-06
 - Add Zfa support. (PR#60)
 - Initial covergroups for Zvk* instructions (PR#61)
@@ -19,7 +21,7 @@ versioned header while the `WIP-DEV` is left empty
 - Add hardcoded register testcases to dataset.cgf and rv32im.cgf
 - Define rs1_val_data for c.ldsp in imc.yaml
 - Update "opcode" to "mnemonics" in the cgf files
-- Delete main.yml 
+- Delete main.yml
 - Update test.yml for CI
 - Define rs1_val_data for instructions from zicfiss.cgf in template.yaml
 - Add "warning" in the verbose definition
@@ -30,7 +32,7 @@ versioned header while the `WIP-DEV` is left empty
 - Add unratified Zaamo subcomponent of A extension
 - Add unratified B extension
 - Fix issues with csr_comb
-- Minor fix in kslraw.u in rv32ip 
+- Minor fix in kslraw.u in rv32ip
 - Fix incorrect 'sig:' entry in aes32dsi in template.yaml
 - Add sig and sz for instructions in template.yaml
 - Minor change of rd definition in c.lui in rv32ec
@@ -69,7 +71,7 @@ versioned header while the `WIP-DEV` is left empty
 
 ## [0.10.2] - 2022-10-20
 - Fixed use of lowercase LI.
-- Fixed correctval to ?? in comments. 
+- Fixed correctval to ?? in comments.
 - Fixed sw to SREG for K tests.
 - Added canaries and signature boundary labels.
 

riscv-ctg/riscv_ctg/data/template.yaml

@@ -10414,7 +10414,129 @@ czero.nez:
 
     // $comment
     // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+cbo.zero:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'RVMODEL_CBZ_BLOCKSIZE'
+  xlen: [32,64]
+  isa:
+    - IZicboz_Zicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs_mx0
+  rs1_val_data: 'gen_usign_dataset(12) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+cbo.clean:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  isa:
+    - IZicbom_Zicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+cbo.flush:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  isa:
+    - IZicbom_Zicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+cbo.inval:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  isa:
+    - IZicbom_Zicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+prefetch.i:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicbop_Zicsr
+  formattype: 'iformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
+    TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
+
+prefetch.r:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicbop_Zicsr
+  formattype: 'iformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
+    TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
+
+prefetch.w:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicbop_Zicsr
+  formattype: 'iformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
+    TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
 
 amoadd.w:
   sig: