Skip to content

v0.4.0

Compare
Choose a tag to compare
@SamuelRiedel SamuelRiedel released this 02 Jul 15:00
· 867 commits to main since this release
1362f97

Added

  • Capability to enable and disable the traces with a CSR
  • CPU model for MemPool in GCC to enable correct instruction scheduling
  • Added GitHub CI flow

Changed

  • Allow atomic extension to be enabled in GCC
  • Replace atomic library with the corresponding builtins
  • Compile all applications in the CI instead of only the ones executed
  • Move Halide applications to their own directory
  • Move linting scripts to scripts folder
  • Move flat hardware dependencies to submodules
  • Updated LLVM to version 12
  • Updated Halide to version 12
  • Run unit tests with Verilator
  • Rename mempool mempool_cluster
  • Restructure software folder

Fixed

  • Stall cycle counting in the trace no longer misses stalls
  • Remove unwanted latches in instruction cache
  • Boot ROM address offset depends on the data width of the ROM