Merge pull request #2850 from o1-labs/sai/store-half-riscv32im

implementation for store half instruction in riscv32im
o1-labs · Dec 19, 2024 · a50442b · a50442b
2 parents 161540c + b0b8760
commit a50442b
Showing 1 changed file with 20 additions and 1 deletion.
diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs
@@ -2064,7 +2064,26 @@ pub fn interpret_stype<Env: InterpreterEnv>(env: &mut Env, instr: SInstruction)
             env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         SInstruction::StoreHalf => {
-            unimplemented!("StoreHalf")
+            // sh: M[x[rs1] + sext(offset)] = x[rs2][15:0]
+            let [v0, v1] = [
+                {
+                    let value_scratch = env.alloc_scratch();
+                    unsafe { env.bitmask(&local_rs2, 8, 0, value_scratch) }
+                },
+                {
+                    let value_scratch = env.alloc_scratch();
+                    unsafe { env.bitmask(&local_rs2, 16, 8, value_scratch) }
+                },
+            ];
+
+            env.lookup_8bits(&v0);
+            env.lookup_8bits(&v1);
+
+            env.write_memory(&address, v0);
+            env.write_memory(&(address.clone() + Env::constant(1u32)), v1);
+
+            env.set_instruction_pointer(next_instruction_pointer.clone());
+            env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         SInstruction::StoreWord => {
             unimplemented!("StoreWord")