Merge pull request #2891 from o1-labs/dw/add-addi-test

o1vm/riscv32im: add example and test for addi

o1vm/resources/programs/riscv32im/src/addi.S

@@ -0,0 +1,20 @@
+.section .text
+.globl _start
+
+_start:
+  # Initialize register
+  li t0, 10         # Load immediate value 10 into t0
+
+  # Perform addition
+  addi t0, t0, 5    # Add 5 to the value in t0 and store the result back in t0
+
+  # Custom exit syscall
+  li a0, 0          # Set a0 to 0
+  li a1, 0          # Set a1 to 0
+  li a2, 0          # Set a2 to 0
+  li a3, 0          # Set a3 to 0
+  li a4, 0          # Set a4 to 0
+  li a5, 0          # Set a5 to 0
+  li a6, 0          # Set a6 to 0
+  li a7, 42         # Set a7 to 42 (custom ecall number)
+  ecall

o1vm/tests/test_riscv_elf.rs

@@ -104,3 +104,19 @@ fn test_sll() {
     // Expected output of the program
     assert_eq!(witness.registers.general_purpose[5], 1 << 14)
 }
+
+#[test]
+fn test_addi() {
+    let curr_dir = std::env::current_dir().unwrap();
+    let path = curr_dir.join(std::path::PathBuf::from(
+        "resources/programs/riscv32im/bin/addi",
+    ));
+    let state = o1vm::elf_loader::parse_riscv32(&path).unwrap();
+    let mut witness = Env::<Fp>::create(PAGE_SIZE.try_into().unwrap(), state);
+
+    while !witness.halt {
+        witness.step();
+    }
+
+    assert_eq!(witness.registers[T0], 15);
+}