Merge pull request #152 from HidetaroTanaka/main

Add SystemVerilog implementation
mawerty · Jan 12, 2024 · d8884a0 · d8884a0
2 parents 38223d9 + e41317e
commit d8884a0
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diff --git a/README.md b/README.md
@@ -113,6 +113,7 @@ Thecoderunsfasterwhentherearenouselessspacesandnewlines.
 - SQL
 - Squirrel
 - Swift
+- SystemVerilog
 - Tcl
 - Toit
 - TrumpScript

diff --git a/implementations/main.sv b/implementations/main.sv
@@ -0,0 +1,11 @@
+module Main #(
+    // specify input bit width
+    parameter N = 32
+)(
+    input logic [N-1:0] x,
+    output logic is_prime
+);
+  always_comb begin
+    is_prime = 1'b0;
+  end
+endmodule
diff --git a/optimized_implementations/main.sv b/optimized_implementations/main.sv
@@ -0,0 +1 @@
+module Main#(parameter N=32)(input logic[N-1:0]x,output logic is_prime);assign is_prime=1'b0;endmodule
-Original file line number
+Diff line change
@@ Expand Up / @@ -113,6 +113,7 @@ Thecoderunsfasterwhentherearenouselessspacesandnewlines. @@
     - SQL
     - Squirrel
     - Swift
+    - SystemVerilog
     - Tcl
     - Toit
     - TrumpScript
@@ Expand Down @@
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		module Main#(parameter N=32)(input logic[N-1:0]x,output logic is_prime);assign is_prime=1'b0;endmodule