Fix mulslw and mululw zero calculation

mamedev · Jan 3, 2025 · fd7af38 · fd7af38
1 parent d274935
commit fd7af38
Showing 1 changed file with 8 additions and 5 deletions.
diff --git a/src/devices/cpu/drcbearm64.cpp b/src/devices/cpu/drcbearm64.cpp
@@ -2728,7 +2728,7 @@ void drcbe_arm64::op_mululw(a64::Assembler &a, const uml::instruction &inst)
 	{
 		a.mrs(TEMP_REG1, a64::Predicate::SysReg::kNZCV);
 
-		a.tst(lo, lo);
+		a.tst(select_register(lo, inst.size()), select_register(lo, inst.size()));
 		a.cset(SCRATCH_REG1, a64::CondCode::kEQ);
 		a.bfi(TEMP_REG1, SCRATCH_REG1, 30, 1); // zero flag
 
@@ -2836,7 +2836,9 @@ void drcbe_arm64::op_mulslw(a64::Assembler &a, const uml::instruction &inst)
 	if ((src1p.is_immediate() && src1p.immediate() == 0) || (src1p.is_immediate() && src1p.immediate() == 0))
 	{
 		a.mov(lo, a64::xzr);
-		a.mov(hi, a64::xzr);
+
+		if (inst.flags() && inst.size() == 8)
+			a.mov(hi, a64::xzr);
 	}
 	else
 	{
@@ -2846,12 +2848,13 @@ void drcbe_arm64::op_mulslw(a64::Assembler &a, const uml::instruction &inst)
 		if (inst.size() == 8)
 		{
 			a.mul(lo, src1, src2);
-			a.smulh(hi, src1, src2);
+
+			if (inst.flags())
+				a.smulh(hi, src1, src2);
 		}
 		else
 		{
 			a.smull(lo, src1.w(), src2.w());
-			a.lsr(hi, lo, 32);
 		}
 	}
 
@@ -2861,7 +2864,7 @@ void drcbe_arm64::op_mulslw(a64::Assembler &a, const uml::instruction &inst)
 	{
 		a.mrs(SCRATCH_REG1, a64::Predicate::SysReg::kNZCV);
 
-		a.tst(lo, lo);
+		a.tst(select_register(lo, inst.size()), select_register(lo, inst.size()));
 		a.cset(TEMP_REG1, a64::CondCode::kEQ);
 		a.bfi(SCRATCH_REG1, TEMP_REG1, 30, 1); // zero flag