crop_vid Module

This repository contains the crop_vid Verilog module, which performs video frame cropping based on user-defined coordinates and dimensions. Additionally, it includes a UVM (Universal Verification Methodology) testbench for verifying the functionality of the module. The testbench utilizes DPI (Direct Programming Interface) to connect to Python for making predictions, and it incorporates coverage and assertions for thorough verification.

Module Description

The crop_vid module is designed to crop video frames by specifying the top-left corner coordinates (crop_x, crop_y) and the dimensions (crop_width, crop_height) of the crop area. The module interfaces with AXI-Stream for both input and output data.

Parameters

• C_S00_AXIS_TDATA_WIDTH: Data width of the AXI Slave Bus Interface (default: 32).
• C_M00_AXIS_TDATA_WIDTH: Data width of the AXI Master Bus Interface (default: 32).
• C_M00_AXIS_START_COUNT: Start count for the AXI Master Bus Interface (default: 32).

Ports

• User-defined Ports:

  • crop_x: X-coordinate of the top-left corner of the crop area.
  • crop_y: Y-coordinate of the top-left corner of the crop area.
  • crop_width: Width of the crop area.
  • crop_height: Height of the crop area.

• AXI Slave Bus Interface (S00_AXIS):

  • s00_axis_aclk: Clock signal.
  • s00_axis_aresetn: Reset signal (active low).
  • s00_axis_tready: Ready signal.
  • s00_axis_tdata: Data signal.
  • s00_axis_tstrb: Strobe signal.
  • s00_axis_tlast: Last signal.
  • s00_axis_tvalid: Valid signal.
  • s00_axis_tuser: User signal.

• AXI Master Bus Interface (M00_AXIS):

  • m00_axis_aclk: Clock signal.
  • m00_axis_aresetn: Reset signal (active low).
  • m00_axis_tvalid: Valid signal.
  • m00_axis_tdata: Data signal.
  • m00_axis_tstrb: Strobe signal.
  • m00_axis_tlast: Last signal.
  • m00_axis_tuser: User signal.
  • m00_axis_tready: Ready signal.

UVM Testbench

The UVM testbench is designed to verify the functionality of the crop_vid module. It uses DPI to connect to Python for making predictions. The testbench also includes coverage metrics and assertions to ensure comprehensive verification.

Features

• DPI Connection: The testbench uses DPI to call Python functions for making predictions during the verification process.
• Coverage: Functional coverage is implemented to ensure all scenarios are tested.
• Assertions: Assertions are added to check critical conditions and ensure the module behaves as expected.

Repository Structure

.
├── hdl
│   ├── crop_vid.v          # Verilog source file for the crop_vid module
│   └── ...                 # Other source files
├── tb
│   ├── dpi                 # dpi library, including `predictor.py` which should be run after compiling and running testbench
│   ├── UVMF                # testbench generated by UVM framework
│   ├── yaml                # yaml files
│   └── ...                 # Other files
├── README.md               # This README file
└── LICENSE                 # license file

Getting Started

Prerequisites

• Verilog Compiler: Questa Sim-64 2021.1.
• UVM Library: UVM library installed.
• Python: Python 2.7 installed.

Running the Simulation

1. Clone the repository:

   git clone [email protected]:mahmoud-amiri/Crop_Video.git
   cd Crop_Video

2. Compile and run the Verilog sources and the UVM testbench:

   ./tb/uvmf/project_benches/crop_video/sim/invoke_questa.bat
   python ./tb/dpi/predictor.py

   change the QUESTA_ROOT and UVMF_HOME path inside invoke_questa.bat.

Contributing

Contributions are welcome! Please open an issue or submit a pull request for any improvements or bug fixes.

License

This project is licensed under the MIT License. See the LICENSE file for details.