alveo_u250: Add PCIe x4 support

litex_boards/platforms/alveo_u250.py

@@ -275,6 +275,17 @@
             "AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")),
     ),
 
+    # pcie
+    ("pcie_x4", 0,
+        Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
+        Subsignal("clk_n", Pins("AM10")),
+        Subsignal("clk_p", Pins("AM11")),
+        Subsignal("rx_n",  Pins("AF1 AG3 AH1 AJ3")),
+        Subsignal("rx_p",  Pins("AF2 AG4 AH2 AJ4")),
+        Subsignal("tx_n",  Pins("AF6 AG8 AH6 AJ8")),
+        Subsignal("tx_p",  Pins("AF7 AG9 AH7 AJ9")),
+    ),
+
     # qsfp28
     ("qsfp28", 0,
         Subsignal("clk_n", Pins("K10")),

litex_boards/targets/alveo_u250.py

@@ -8,7 +8,7 @@
 # Copyright (c) 2020 David Shah <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
-import argparse
+import argparse, os
 
 from migen import *
 
@@ -23,6 +23,12 @@
 from litedram.modules import MTA18ASF2G72PZ
 from litedram.phy import usddrphy
 
+from litepcie.phy.usppciephy import USPPCIEPHY
+from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
+from litepcie.frontend.dma import LitePCIeDMA
+from litepcie.frontend.wishbone import LitePCIeWishboneBridge
+from litepcie.software import generate_litepcie_software
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -54,7 +60,7 @@ def __init__(self, platform, sys_clk_freq):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
         platform = alveo_u250.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -88,6 +94,44 @@ def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
         self.add_ram("firmware_ram", 0x20000000, 0x8000)
 
+        # PCIe -------------------------------------------------------------------------------------
+        if with_pcie:
+            # PHY
+            self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
+                data_width = 128,
+                bar0_size  = 0x20000)
+            #self.pcie_phy.add_timing_constraints(platform) # FIXME
+            platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
+            self.add_csr("pcie_phy")
+
+            # Endpoint
+            self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
+
+            # Wishbone bridge
+            self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
+                base_address = self.mem_map["csr"])
+            self.add_wb_master(self.pcie_bridge.wishbone)
+
+            # DMA0
+            self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
+                with_buffering = True, buffering_depth=1024,
+                with_loopback  = True)
+            self.add_csr("pcie_dma0")
+
+            self.add_constant("DMA_CHANNELS", 1)
+
+            # MSI
+            self.submodules.pcie_msi = LitePCIeMSI()
+            self.add_csr("pcie_msi")
+            self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
+            self.interrupts = {
+                "PCIE_DMA0_WRITER":    self.pcie_dma0.writer.irq,
+                "PCIE_DMA0_READER":    self.pcie_dma0.reader.irq,
+            }
+            for i, (k, v) in enumerate(sorted(self.interrupts.items())):
+                self.comb += self.pcie_msi.irqs[i].eq(v)
+                self.add_constant(k + "_INTERRUPT", i)
+
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led"),
@@ -99,15 +143,23 @@ def __init__(self, sys_clk_freq=int(125e6), **kwargs):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
+    parser.add_argument("--driver",    action="store_true", help="Generate PCIe driver")
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(**soc_sdram_argdict(args))
+    # Enforce arguments
+    args.csr_data_width = 32
+
+    soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
+    if args.driver:
+        generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
+
     if args.load:
         prog = soc.platform.create_programmer()
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))