dhis2: verify (lib)

fix: refine chip margin logic #3760

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Run time

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Job	Run time
build	4m 0s
test	1m 32s
lint	1m 31s
e2e (1)	8m 23s
e2e (2)	8m 20s
e2e (3)	8m 16s
e2e (4)	8m 17s
publish	1m 27s
	41m 46s