Try to add vstr semantic

cea-sec · Sep 9, 2021 · e08c21d · e08c21d
1 parent b2b0b43
commit e08c21d
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Showing 2 changed files with 19 additions and 3 deletions.
diff --git a/miasm/arch/arm/sem.py b/miasm/arch/arm/sem.py
@@ -972,7 +972,6 @@ def blx(ir, instr, a):
     e.append(ExprAssign(LR, l))
     return e, []
 
-# todo
 def vmov(ir, instr, a, b, c=None):
     e = []
     if c is None:
@@ -996,9 +995,20 @@ def vmov(ir, instr, a, b, c=None):
 
     return e, []
 
-# todo
 def vstr(ir, instr, a, b):
-    raise NotImplementedError('Not implemented')
+    e = []
+    if a in spregs_expr:
+        e.append(ExprAssign(b, a))
+    elif a in dpregs_expr:
+        if instr.mode == 'l':
+            e.append(ExprAssign(b, a[:32]))
+            e.append(ExprAssign(ExprMem(b.ptr + ExprInt(4, 32), 32), a[32:]))
+        else:
+            e.append(ExprAssign(b, a[32:]))
+            e.append(ExprAssign(b, a[:32]))
+    else:
+        raise NotImplementedError('Not implemented')
+    return e, []
 
 # todo
 def vcvt(ir, instr, a, b):

diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py
@@ -506,6 +506,12 @@ def test_vmov(self):
         self.assertEqual(compute_t('VMOV R0, S0', {S0: 0x1, R0: 0x2}), {S0: 0x1, R0: 0x1})
         self.assertEqual(compute_t('VMOV D0, R0, R1', {D0: 0x1, R0: 0x2, R1:0x3}), {D0: 0x2 | (0x3 << 32), R0: 0x2, R1: 0x3})
         self.assertEqual(compute_t('VMOV R0, R1, D0', {D0: 0xfffffffcfffffffe, R0: 0x2, R1:0x3}), {D0: 0xfffffffcfffffffe, R0: 0xfffffffe, R1: 0xfffffffc})
+        self.assertEqual(compute_t('VSTR S0, [SP, 0x30]',
+        {S0: 0x10000, SP: 0x20000, ExprMem(ExprOp('preinc', ExprInt(0x20000, 32), ExprInt(0x30, 32)), 32): 0x50}), 
+        {S0: 0x10000, SP: 0x20000, ExprMem(ExprOp('preinc', ExprInt(0x20000, 32), ExprInt(0x30, 32)), 32): 0x10000})
+        self.assertEqual(compute_t('VSTR D0, [SP, 0x30]',
+        {D0: 0x1000000020000000, SP: 0x20000, ExprMem(ExprOp('preinc', ExprInt(0x20000, 32), ExprInt(0x30, 32)), 32): 0x50      , ExprMem(ExprOp('+', ExprOp('preinc', ExprInt(0x20000, 32), ExprInt(0x30, 32)), ExprInt(4, 32)), 32): 0x50}), 
+        {D0: 0x1000000020000000, SP: 0x20000, ExprMem(ExprOp('preinc', ExprInt(0x20000, 32), ExprInt(0x30, 32)), 32): 0x20000000, ExprMem(ExprOp('+', ExprOp('preinc', ExprInt(0x20000, 32), ExprInt(0x30, 32)), ExprInt(4, 32)), 32): 0x10000000})
 
 if __name__ == '__main__':
     testsuite = unittest.TestLoader().loadTestsFromTestCase(TestARMSemantic)