digest: Only use AVX implementations on Intel CPUs.

briansmith · Jan 14, 2025 · 6967329 · 6967329
1 parent 303ca7e
commit 6967329
Show file tree

Hide file tree

Showing 3 changed files with 15 additions and 4 deletions.
diff --git a/src/cpu/intel.rs b/src/cpu/intel.rs
@@ -134,6 +134,13 @@ impl_get_feature! { SSSE3 => Ssse3 }
 
 cfg_if! {
     if #[cfg(any(target_arch = "x86_64"))] {
+        //
+        const INTEL_CPU: Feature = Feature {
+            word: 0,
+            mask: 1 << 30,
+        };
+        impl_get_feature!{ INTEL_CPU => IntelCpu }
+
         pub(crate) const MOVBE: Feature = Feature {
             word: 1,
             mask: 1 << 22,

diff --git a/src/digest/sha2/sha2_32.rs b/src/digest/sha2/sha2_32.rs
@@ -37,11 +37,13 @@ pub(crate) fn block_data_order_32(
         } else if #[cfg(all(target_arch = "arm", target_endian = "little"))] {
             sha2_32_ffi!(unsafe { cpu::Features => sha256_block_data_order }, state, data, cpu)
         } else if #[cfg(target_arch = "x86_64")] {
-            use cpu::{GetFeature as _, intel::{Sha, Avx, Ssse3 }};
+            use cpu::{GetFeature as _, intel::{Avx, IntelCpu, Sha, Ssse3 }};
             if let Some(cpu) = cpu.get_feature() {
                 sha2_32_ffi!(unsafe { (Sha, Ssse3) => sha256_block_data_order_hw }, state, data, cpu)
             } else if let Some(cpu) = cpu.get_feature() {
-                sha2_32_ffi!(unsafe { Avx => sha256_block_data_order_avx }, state, data, cpu)
+                // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA
+                // extension; see the discussion in upstream's sha1-586.pl.
+                sha2_32_ffi!(unsafe { (Avx, IntelCpu) => sha256_block_data_order_avx }, state, data, cpu)
             } else if let Some(cpu) = cpu.get_feature() {
                 sha2_32_ffi!(unsafe { Ssse3 => sha256_block_data_order_ssse3 }, state, data, cpu)
             } else {

diff --git a/src/digest/sha2/sha2_64.rs b/src/digest/sha2/sha2_64.rs
@@ -37,9 +37,11 @@ pub(crate) fn block_data_order_64(
         } else if #[cfg(all(target_arch = "arm", target_endian = "little"))] {
             sha2_64_ffi!(unsafe { cpu::Features => sha512_block_data_order }, state, data, cpu)
         } else if #[cfg(target_arch = "x86_64")] {
-            use cpu::{GetFeature as _, intel::Avx};
+            use cpu::{GetFeature as _, intel::{IntelCpu, Avx}};
             if let Some(cpu) = cpu.get_feature() {
-                sha2_64_ffi!(unsafe { Avx => sha512_block_data_order_avx }, state, data, cpu)
+                // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA
+                // extension; see the discussion in upstream's sha1-586.pl.
+                sha2_64_ffi!(unsafe { (Avx, IntelCpu) => sha512_block_data_order_avx }, state, data, cpu)
             } else {
                 sha2_64_ffi!(unsafe { () => sha512_block_data_order_nohw }, state, data, ())
             }