Skip to content

Commit

Permalink
Update README.md
Browse files Browse the repository at this point in the history
  • Loading branch information
lastweek authored Jan 25, 2022
1 parent af00df3 commit e6c9170
Showing 1 changed file with 14 additions and 6 deletions.
20 changes: 14 additions & 6 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,11 +1,17 @@
# Clio Artifact
# Clio System

Clio is a Hardware-Software Co-Designed Disaggregated Memory System.
The paper has been accepted to ASPLOS'22.
We are still working on the final version.
You can find a pre-publication version [here](https://arxiv.org/pdf/2108.03492.pdf).
Clio is a disaggregated memory system that virtualizes,
protects, and manages disaggregated memory at hardware-based
memory nodes. More details in our ASPLOS'22 paper [here](https://arxiv.org/pdf/2108.03492.pdf).

**ASPLOS'22 Artifact Evaluators, please see [Documentation/asplos-ae.md](./Documentation/asplos-ae.md).**
This repo contains Clio's FPGA hardware design, host side software, and testing program.

## System Architetcure

The Clio hardware includes a new virtual memory
system, a customized network system, and a framework for computation offloading

<img src="Documentation/arch.png" alt="drawing" width="500"/>

## Documentation

Expand All @@ -17,6 +23,8 @@ To run Clio, see [Documentation/run.md](./Documentation/run.md).

To debug Clio, see [Documentation/debug.md](./Documentation/debug.md).

**ASPLOS'22 Artifact Evaluators, please see [Documentation/asplos-ae.md](./Documentation/asplos-ae.md).**

## Repo Layout

High-level layout:
Expand Down

0 comments on commit e6c9170

Please sign in to comment.