Zvbb: support Zvbb instructions (#105)

* encoding: add opcode for Zvbb

* Zvbb: add FuOpcode

* func(Zvbb): add Zvbb code

* Zvbb: support vbrev.v, vbrev8.v, vrev8.v, vclz.v, vctz.v, vcpop.v

* Zvbb: support vrol.vv and vrol.vx

* Zvbb: support vror.vv, vror.vx and vror.vi

* Zvbb: fix format for vro and vcount

* Zvbb: support vwsll.vv vwsll.vx and vwsll.vi

* Zvbb: fix result wrong for vctz.v instruction

* Zvbb: fix FuOpcode for vror instruction

* Zvbb: refactor vrol and vror instruction

* vfalu: fix condition of result selection for vmv.v.v instruction

* Zvbb: fix count result when vs2 = 0 for vclz.v and vctz.v instruction

* Zvbb: modify the shift logic of vrol, vror and vwsll instruction

src/main/scala/yunsuan/encoding/Opcode/VialuOpcode.scala

@@ -39,4 +39,14 @@ object VialuOpcode {
   def vssrl  = 31.U(width.W)
   def vssra  = 32.U(width.W)
   def vmvsx  = 46.U(width.W)
+  // Zvbb
+  def vcpop  = 39.U(width.W)
+  def vbrev  = 48.U(width.W)
+  def vbrev8 = 49.U(width.W)
+  def vrev8  = 50.U(width.W)
+  def vclz   = 51.U(width.W)
+  def vctz   = 52.U(width.W)
+  def vrol   = 53.U(width.W)
+  def vror   = 54.U(width.W)
+  def vwsll  = 55.U(width.W)
 }

src/main/scala/yunsuan/package.scala

@@ -176,6 +176,17 @@ package object yunsuan {
     def vmorn_mm    = LiteralCat(FMT.MMM  , UINT, VialuOpcode.vorn)   // "b10_0_001101".U(OpTypeWidth.W) // vorn
     def vmxnor_mm   = LiteralCat(FMT.MMM  , UINT, VialuOpcode.vxnor)  // "b10_0_001110".U(OpTypeWidth.W) // vxnor
     def vmv_s_x     = LiteralCat(FMT.ZXV  , SINT, VialuOpcode.vmvsx)  // "b00_1_101110".U(OpTypeWidth.W) // vmvsx
+    // Zvbb
+    def vandn_vv    = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vandn)  // "b00_0_001001".U(OPTypeWidth.W) // vandn
+    def vbrev_v     = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vbrev)  // "b00_0_101111".U(OpTypeWidth.W) // vbrev
+    def vbrev8_v    = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vbrev8) // "b00_0_110000".U(OpTypeWidth.W) // vbrev8
+    def vrev8_v     = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vrev8)  // "b00_0_110001".U(OpTypeWidth.W) // vrev8
+    def vclz_v      = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vclz)   // "b00_0_110010".U(OpTypeWidth.W) // vclz
+    def vctz_v      = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vctz)   // "b00_0_110011".U(OpTypeWidth.W) // vctz
+    def vcpop_v     = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vcpop)  // "b00_0_110100".U(OpTypeWidth.W) // vcpop
+    def vrol_vv     = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vrol)   // "b00_0_110101".U(OpTypeWidth.W) // vrol
+    def vror_vv     = LiteralCat(FMT.VVV  , UINT, VialuOpcode.vror)   // "b00_0_110110".U(OpTypeWidth.W) // vror
+    def vwsll_vv    = LiteralCat(FMT.WVW  , UINT, VialuOpcode.vwsll)  // "b10_0_110111".U(OpTypeWidth.W) // vwsll
 
     def getOpcode(fuOpType: UInt) : UInt = fuOpType(5, 0)
 

src/main/scala/yunsuan/vector/VectorALU/VAluBundles.scala

@@ -52,13 +52,26 @@ class VAluOpcode extends Bundle{
   def isIntFixp = op < vredsum || op === vmvsx
   def isVmvsx = op === vmvsx
   def isVmvxs = op === vmvxs
+  def isVmergeMove = op === vmerge || op === vmv || op === vmvsx
   // IMac opcode:
   def op3b = op(2, 0)
   def highHalf = op3b === 1.U
   def isMacc = op3b === 2.U || op3b === 3.U || op3b === 4.U || op3b === 5.U
   def isSub = op3b === 3.U || op3b === 5.U
   def isFixP = op3b === 6.U
   def overWriteMultiplicand = op3b === 4.U || op3b === 5.U
+  // Zvbb opcode:
+  def isVbrev   = op === vbrev
+  def isVbrev8  = op === vbrev8
+  def isVrev8   = op === vrev8
+  def isClz     = op === vclz
+  def isCtz     = op === vctz
+  def isVrol    = op === vrol
+  def isVror    = op === vror
+  def isVwsll   = op === vwsll
+  def isVrev    = op === vbrev || op === vbrev8 || op === vrev8
+  def isVCount  = op === vclz || op === vctz || op === vcpop
+  def isVro     = op === vrol || op === vror
 }
 
 class VIFuInfo extends Bundle {

src/main/scala/yunsuan/vector/VectorALU/VAluDecode.scala

@@ -54,6 +54,15 @@ object VAluOpcode {
   val vid     = 45.U(6.W)
   val vmvsx   = 46.U(6.W)
   val vmvxs   = 47.U(6.W)
+  // Zvbb
+  val vbrev   = 48.U(6.W)
+  val vbrev8  = 49.U(6.W)
+  val vrev8   = 50.U(6.W)
+  val vclz    = 51.U(6.W)
+  val vctz    = 52.U(6.W)
+  val vrol    = 53.U(6.W)
+  val vror    = 54.U(6.W)
+  val vwsll   = 55.U(6.W)
 }
 
 import VAluOpcode._