vfcvt: fix cvt32 result reg use fireReg as enable condition

OpenXiangShan · Mar 11, 2024 · 526bfa6 · 526bfa6
1 parent 1def82c
commit 526bfa6
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Showing 2 changed files with 8 additions and 8 deletions.
diff --git a/src/main/scala/yunsuan/vector/VectorConvert/CVT16.scala b/src/main/scala/yunsuan/vector/VectorConvert/CVT16.scala
@@ -46,9 +46,9 @@ class CVT16(width: Int = 16) extends CVT(width){
   val fflags = WireInit(Cat(NV, DZ, OF, UF, NX))
 
   val result0 = Wire(UInt(16.W))
-  val result0_reg0 = RegEnable(result0, 0.U(16.W), fireReg)
+  val result0_reg1 = RegEnable(result0, 0.U(16.W), fireReg)
   val fflags0 = WireInit(Cat(NV, DZ, OF, UF, NX))
-  val fflags0_reg0 = RegEnable(fflags0, fireReg)
+  val fflags0_reg1 = RegEnable(fflags0, fireReg)
 
   val round_in = Wire(UInt(11.W))
   val round_roundIn = Wire(Bool())
@@ -507,8 +507,8 @@ class CVT16(width: Int = 16) extends CVT(width){
   )
 
   // cycle2
-  result := result0_reg0
-  fflags := fflags0_reg0
+  result := result0_reg1
+  fflags := fflags0_reg1
 
   io.result := result
   io.fflags := fflags

diff --git a/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala b/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala
@@ -51,9 +51,9 @@ class CVT32(width: Int = 32) extends CVT(width){
   val fflags = WireInit(Cat(NV, DZ, OF, UF, NX))
 
   val result0 = Wire(UInt(32.W))
-  val result0_reg0 = RegEnable(result0, 0.U(32.W), fire)
+  val result0_reg1 = RegEnable(result0, 0.U(32.W), fireReg)
   val fflags0 = WireInit(Cat(NV, DZ, OF, UF, NX))
-  val fflags0_reg0 = RegEnable(fflags0, fire)
+  val fflags0_reg1 = RegEnable(fflags0, fireReg)
 
   val round_in = Wire(UInt(24.W))
   val round_roundIn = Wire(Bool())
@@ -1160,8 +1160,8 @@ class CVT32(width: Int = 32) extends CVT(width){
   )
 
   // cycle2
-  result := result0_reg0
-  fflags := fflags0_reg0
+  result := result0_reg1
+  fflags := fflags0_reg1
 
   io.result := result
   io.fflags := fflags