Skip to content

Commit

Permalink
Merge pull request #130 from xiaofeibao-xjtu/cnan
Browse files Browse the repository at this point in the history
VFExu: FpCanonicalNAN is not SNAN
  • Loading branch information
lewislzh authored May 8, 2024
2 parents dd92046 + d79e14d commit 4c33741
Show file tree
Hide file tree
Showing 4 changed files with 51 additions and 51 deletions.
12 changes: 6 additions & 6 deletions src/main/scala/yunsuan/vector/VectorFloatAdder.scala
Original file line number Diff line number Diff line change
Expand Up @@ -468,9 +468,9 @@ class FloatAdderF32WidenF16MixedPipeline(val is_print:Boolean = false,val hasMin
io.fp_b(30,23).andR
)
val fp_a_is_NAN = io.fp_aIsFpCanonicalNAN | Efp_a_is_all_one & fp_a_mantissa_isnot_zero
val fp_a_is_SNAN = io.fp_aIsFpCanonicalNAN | Efp_a_is_all_one & fp_a_mantissa_isnot_zero & !fp_a_to32(significandWidth-2)
val fp_a_is_SNAN = Efp_a_is_all_one & fp_a_mantissa_isnot_zero & !fp_a_to32(significandWidth-2)
val fp_b_is_NAN = io.fp_bIsFpCanonicalNAN | Efp_b_is_all_one & fp_b_mantissa_isnot_zero
val fp_b_is_SNAN = io.fp_bIsFpCanonicalNAN | Efp_b_is_all_one & fp_b_mantissa_isnot_zero & !fp_b_to32(significandWidth-2)
val fp_b_is_SNAN = Efp_b_is_all_one & fp_b_mantissa_isnot_zero & !fp_b_to32(significandWidth-2)
val fp_a_is_infinite = Efp_a_is_all_one & (!fp_a_mantissa_isnot_zero)
val fp_b_is_infinite = Efp_b_is_all_one & (!fp_b_mantissa_isnot_zero)
val fp_a_is_zero = Efp_a_is_zero & !fp_a_mantissa_isnot_zero
Expand Down Expand Up @@ -1772,9 +1772,9 @@ class FloatAdderF64WidenPipeline(val is_print:Boolean = false,val hasMinMaxCompa
val Efp_a_is_all_one = Efp_a.andR | (fp_a_is_f32 & Efp_a==="b10001111111".U)
val Efp_b_is_all_one = Efp_b.andR | (fp_b_is_f32 & Efp_b==="b10001111111".U)
val fp_a_is_NAN = io.fp_aIsFpCanonicalNAN | Efp_a_is_all_one & fp_a_mantissa_isnot_zero
val fp_a_is_SNAN = io.fp_aIsFpCanonicalNAN | Efp_a_is_all_one & fp_a_mantissa_isnot_zero & !fp_a_to64(significandWidth-2)
val fp_a_is_SNAN = Efp_a_is_all_one & fp_a_mantissa_isnot_zero & !fp_a_to64(significandWidth-2)
val fp_b_is_NAN = io.fp_bIsFpCanonicalNAN | Efp_b_is_all_one & fp_b_mantissa_isnot_zero
val fp_b_is_SNAN = io.fp_bIsFpCanonicalNAN | Efp_b_is_all_one & fp_b_mantissa_isnot_zero & !fp_b_to64(significandWidth-2)
val fp_b_is_SNAN = Efp_b_is_all_one & fp_b_mantissa_isnot_zero & !fp_b_to64(significandWidth-2)
val fp_a_is_infinite = Efp_a_is_all_one & (!fp_a_mantissa_isnot_zero)
val fp_b_is_infinite = Efp_b_is_all_one & (!fp_b_mantissa_isnot_zero)
val fp_a_is_zero = Efp_a_is_zero & !fp_a_mantissa_isnot_zero
Expand Down Expand Up @@ -2452,9 +2452,9 @@ class FloatAdderF16Pipeline(val is_print:Boolean = false,val hasMinMaxCompare:Bo
val fp_a_mantissa_isnot_zero = io.fp_a.tail(1 + exponentWidth).orR
val fp_b_mantissa_isnot_zero = io.fp_b.tail(1 + exponentWidth).orR
val fp_a_is_NAN = io.fp_aIsFpCanonicalNAN | Efp_a_is_all_one & fp_a_mantissa_isnot_zero
val fp_a_is_SNAN = io.fp_aIsFpCanonicalNAN | Efp_a_is_all_one & fp_a_mantissa_isnot_zero & !io.fp_a(significandWidth-2)
val fp_a_is_SNAN = Efp_a_is_all_one & fp_a_mantissa_isnot_zero & !io.fp_a(significandWidth-2)
val fp_b_is_NAN = io.fp_bIsFpCanonicalNAN | Efp_b_is_all_one & fp_b_mantissa_isnot_zero
val fp_b_is_SNAN = io.fp_bIsFpCanonicalNAN | Efp_b_is_all_one & fp_b_mantissa_isnot_zero & !io.fp_b(significandWidth-2)
val fp_b_is_SNAN = Efp_b_is_all_one & fp_b_mantissa_isnot_zero & !io.fp_b(significandWidth-2)
val fp_a_is_infinite = Efp_a_is_all_one & (!fp_a_mantissa_isnot_zero)
val fp_b_is_infinite = Efp_b_is_all_one & (!fp_b_mantissa_isnot_zero)
val float_adder_fflags = Wire(UInt(5.W))
Expand Down
32 changes: 16 additions & 16 deletions src/main/scala/yunsuan/vector/VectorFloatDivider.scala
Original file line number Diff line number Diff line change
Expand Up @@ -390,22 +390,22 @@ class VectorFloatDividerR64() extends Module {
val opb_is_inf_f32_1 = opb_exp_is_max_f32_1 & opb_frac_is_zero_f32_1
val opb_is_inf_f16_2 = opb_exp_is_max_f16_2 & opb_frac_is_zero_f16_2
val opb_is_inf_f16_3 = opb_exp_is_max_f16_3 & opb_frac_is_zero_f16_3
val opa_is_qnan_f64_0 = opa_exp_is_max_f64_0 & opa_frac_f64_0.head(1).asBool
val opa_is_qnan_f32_1 = opa_exp_is_max_f32_1 & opa_frac_f32_1.head(1).asBool
val opa_is_qnan_f16_2 = opa_exp_is_max_f16_2 & opa_frac_f16_2.head(1).asBool
val opa_is_qnan_f16_3 = opa_exp_is_max_f16_3 & opa_frac_f16_3.head(1).asBool
val opb_is_qnan_f64_0 = opb_exp_is_max_f64_0 & opb_frac_f64_0.head(1).asBool
val opb_is_qnan_f32_1 = opb_exp_is_max_f32_1 & opb_frac_f32_1.head(1).asBool
val opb_is_qnan_f16_2 = opb_exp_is_max_f16_2 & opb_frac_f16_2.head(1).asBool
val opb_is_qnan_f16_3 = opb_exp_is_max_f16_3 & opb_frac_f16_3.head(1).asBool
val opa_is_snan_f64_0 = io.fp_aIsFpCanonicalNAN |opa_exp_is_max_f64_0 & !opa_frac_f64_0.head(1).asBool & !opa_frac_is_zero_f64_0
val opa_is_snan_f32_1 = io.fp_aIsFpCanonicalNAN |opa_exp_is_max_f32_1 & !opa_frac_f32_1.head(1).asBool & !opa_frac_is_zero_f32_1
val opa_is_snan_f16_2 = io.fp_aIsFpCanonicalNAN |opa_exp_is_max_f16_2 & !opa_frac_f16_2.head(1).asBool & !opa_frac_is_zero_f16_2
val opa_is_snan_f16_3 = io.fp_aIsFpCanonicalNAN |opa_exp_is_max_f16_3 & !opa_frac_f16_3.head(1).asBool & !opa_frac_is_zero_f16_3
val opb_is_snan_f64_0 = io.fp_bIsFpCanonicalNAN |opb_exp_is_max_f64_0 & !opb_frac_f64_0.head(1).asBool & !opb_frac_is_zero_f64_0
val opb_is_snan_f32_1 = io.fp_bIsFpCanonicalNAN |opb_exp_is_max_f32_1 & !opb_frac_f32_1.head(1).asBool & !opb_frac_is_zero_f32_1
val opb_is_snan_f16_2 = io.fp_bIsFpCanonicalNAN |opb_exp_is_max_f16_2 & !opb_frac_f16_2.head(1).asBool & !opb_frac_is_zero_f16_2
val opb_is_snan_f16_3 = io.fp_bIsFpCanonicalNAN |opb_exp_is_max_f16_3 & !opb_frac_f16_3.head(1).asBool & !opb_frac_is_zero_f16_3
val opa_is_qnan_f64_0 = io.fp_aIsFpCanonicalNAN | opa_exp_is_max_f64_0 & opa_frac_f64_0.head(1).asBool
val opa_is_qnan_f32_1 = io.fp_aIsFpCanonicalNAN | opa_exp_is_max_f32_1 & opa_frac_f32_1.head(1).asBool
val opa_is_qnan_f16_2 = io.fp_aIsFpCanonicalNAN | opa_exp_is_max_f16_2 & opa_frac_f16_2.head(1).asBool
val opa_is_qnan_f16_3 = io.fp_aIsFpCanonicalNAN | opa_exp_is_max_f16_3 & opa_frac_f16_3.head(1).asBool
val opb_is_qnan_f64_0 = io.fp_bIsFpCanonicalNAN | opb_exp_is_max_f64_0 & opb_frac_f64_0.head(1).asBool
val opb_is_qnan_f32_1 = io.fp_bIsFpCanonicalNAN | opb_exp_is_max_f32_1 & opb_frac_f32_1.head(1).asBool
val opb_is_qnan_f16_2 = io.fp_bIsFpCanonicalNAN | opb_exp_is_max_f16_2 & opb_frac_f16_2.head(1).asBool
val opb_is_qnan_f16_3 = io.fp_bIsFpCanonicalNAN | opb_exp_is_max_f16_3 & opb_frac_f16_3.head(1).asBool
val opa_is_snan_f64_0 = opa_exp_is_max_f64_0 & !opa_frac_f64_0.head(1).asBool & !opa_frac_is_zero_f64_0
val opa_is_snan_f32_1 = opa_exp_is_max_f32_1 & !opa_frac_f32_1.head(1).asBool & !opa_frac_is_zero_f32_1
val opa_is_snan_f16_2 = opa_exp_is_max_f16_2 & !opa_frac_f16_2.head(1).asBool & !opa_frac_is_zero_f16_2
val opa_is_snan_f16_3 = opa_exp_is_max_f16_3 & !opa_frac_f16_3.head(1).asBool & !opa_frac_is_zero_f16_3
val opb_is_snan_f64_0 = opb_exp_is_max_f64_0 & !opb_frac_f64_0.head(1).asBool & !opb_frac_is_zero_f64_0
val opb_is_snan_f32_1 = opb_exp_is_max_f32_1 & !opb_frac_f32_1.head(1).asBool & !opb_frac_is_zero_f32_1
val opb_is_snan_f16_2 = opb_exp_is_max_f16_2 & !opb_frac_f16_2.head(1).asBool & !opb_frac_is_zero_f16_2
val opb_is_snan_f16_3 = opb_exp_is_max_f16_3 & !opb_frac_f16_3.head(1).asBool & !opb_frac_is_zero_f16_3
val opa_is_nan_f64_0 = opa_is_qnan_f64_0 | opa_is_snan_f64_0
val opa_is_nan_f32_1 = opa_is_qnan_f32_1 | opa_is_snan_f32_1
val opa_is_nan_f16_2 = opa_is_qnan_f16_2 | opa_is_snan_f16_2
Expand Down
42 changes: 21 additions & 21 deletions src/main/scala/yunsuan/vector/VectorFloatFMA.scala
Original file line number Diff line number Diff line change
Expand Up @@ -1080,27 +1080,27 @@ class VectorFloatFMA() extends Module{
val fp_c_is_nan_f16_2 = io.fp_cIsFpCanonicalNAN | Ec_f16_2.andR & fp_c_significand_f16_2.tail(1).orR
val fp_c_is_nan_f16_3 = io.fp_cIsFpCanonicalNAN | Ec_f16_3.andR & fp_c_significand_f16_3.tail(1).orR

val fp_a_is_snan_f64 = io.fp_aIsFpCanonicalNAN | Mux(io.res_widening & is_fp64,widen_Ea_f32_0.andR,Ea_f64.andR ) & !fp_a_significand_f64.tail(1).head(1) & fp_a_significand_f64.tail(2).orR
val fp_a_is_snan_f32_0 = io.fp_aIsFpCanonicalNAN | Mux(io.res_widening & is_fp32,widen_Ea_f16_0.andR,Ea_f32_0.andR) & !fp_a_significand_f32_0.tail(1).head(1) & fp_a_significand_f32_0.tail(2).orR
val fp_a_is_snan_f32_1 = io.fp_aIsFpCanonicalNAN | Mux(io.res_widening & is_fp32,widen_Ea_f16_1.andR,Ea_f32_1.andR) & !fp_a_significand_f32_1.tail(1).head(1) & fp_a_significand_f32_1.tail(2).orR
val fp_a_is_snan_f16_0 = io.fp_aIsFpCanonicalNAN | Ea_f16_0.andR & !fp_a_significand_f16_0.tail(1).head(1) & fp_a_significand_f16_0.tail(2).orR
val fp_a_is_snan_f16_1 = io.fp_aIsFpCanonicalNAN | Ea_f16_1.andR & !fp_a_significand_f16_1.tail(1).head(1) & fp_a_significand_f16_1.tail(2).orR
val fp_a_is_snan_f16_2 = io.fp_aIsFpCanonicalNAN | Ea_f16_2.andR & !fp_a_significand_f16_2.tail(1).head(1) & fp_a_significand_f16_2.tail(2).orR
val fp_a_is_snan_f16_3 = io.fp_aIsFpCanonicalNAN | Ea_f16_3.andR & !fp_a_significand_f16_3.tail(1).head(1) & fp_a_significand_f16_3.tail(2).orR
val fp_b_is_snan_f64 = io.fp_bIsFpCanonicalNAN | Mux(io.res_widening & is_fp64,widen_Eb_f32_0.andR,Eb_f64.andR ) & !fp_b_significand_f64.tail(1).head(1) & fp_b_significand_f64.tail(2).orR
val fp_b_is_snan_f32_0 = io.fp_bIsFpCanonicalNAN | Mux(io.res_widening & is_fp32,widen_Eb_f16_0.andR,Eb_f32_0.andR) & !fp_b_significand_f32_0.tail(1).head(1) & fp_b_significand_f32_0.tail(2).orR
val fp_b_is_snan_f32_1 = io.fp_bIsFpCanonicalNAN | Mux(io.res_widening & is_fp32,widen_Eb_f16_1.andR,Eb_f32_1.andR) & !fp_b_significand_f32_1.tail(1).head(1) & fp_b_significand_f32_1.tail(2).orR
val fp_b_is_snan_f16_0 = io.fp_bIsFpCanonicalNAN | Eb_f16_0.andR & !fp_b_significand_f16_0.tail(1).head(1) & fp_b_significand_f16_0.tail(2).orR
val fp_b_is_snan_f16_1 = io.fp_bIsFpCanonicalNAN | Eb_f16_1.andR & !fp_b_significand_f16_1.tail(1).head(1) & fp_b_significand_f16_1.tail(2).orR
val fp_b_is_snan_f16_2 = io.fp_bIsFpCanonicalNAN | Eb_f16_2.andR & !fp_b_significand_f16_2.tail(1).head(1) & fp_b_significand_f16_2.tail(2).orR
val fp_b_is_snan_f16_3 = io.fp_bIsFpCanonicalNAN | Eb_f16_3.andR & !fp_b_significand_f16_3.tail(1).head(1) & fp_b_significand_f16_3.tail(2).orR
val fp_c_is_snan_f64 = io.fp_cIsFpCanonicalNAN | Ec_f64.andR & !fp_c_significand_f64.tail(1).head(1) & fp_c_significand_f64.tail(2).orR
val fp_c_is_snan_f32_0 = io.fp_cIsFpCanonicalNAN | Ec_f32_0.andR & !fp_c_significand_f32_0.tail(1).head(1) & fp_c_significand_f32_0.tail(2).orR
val fp_c_is_snan_f32_1 = io.fp_cIsFpCanonicalNAN | Ec_f32_1.andR & !fp_c_significand_f32_1.tail(1).head(1) & fp_c_significand_f32_1.tail(2).orR
val fp_c_is_snan_f16_0 = io.fp_cIsFpCanonicalNAN | Ec_f16_0.andR & !fp_c_significand_f16_0.tail(1).head(1) & fp_c_significand_f16_0.tail(2).orR
val fp_c_is_snan_f16_1 = io.fp_cIsFpCanonicalNAN | Ec_f16_1.andR & !fp_c_significand_f16_1.tail(1).head(1) & fp_c_significand_f16_1.tail(2).orR
val fp_c_is_snan_f16_2 = io.fp_cIsFpCanonicalNAN | Ec_f16_2.andR & !fp_c_significand_f16_2.tail(1).head(1) & fp_c_significand_f16_2.tail(2).orR
val fp_c_is_snan_f16_3 = io.fp_cIsFpCanonicalNAN | Ec_f16_3.andR & !fp_c_significand_f16_3.tail(1).head(1) & fp_c_significand_f16_3.tail(2).orR
val fp_a_is_snan_f64 = Mux(io.res_widening & is_fp64,widen_Ea_f32_0.andR,Ea_f64.andR ) & !fp_a_significand_f64.tail(1).head(1) & fp_a_significand_f64.tail(2).orR
val fp_a_is_snan_f32_0 = Mux(io.res_widening & is_fp32,widen_Ea_f16_0.andR,Ea_f32_0.andR) & !fp_a_significand_f32_0.tail(1).head(1) & fp_a_significand_f32_0.tail(2).orR
val fp_a_is_snan_f32_1 = Mux(io.res_widening & is_fp32,widen_Ea_f16_1.andR,Ea_f32_1.andR) & !fp_a_significand_f32_1.tail(1).head(1) & fp_a_significand_f32_1.tail(2).orR
val fp_a_is_snan_f16_0 = Ea_f16_0.andR & !fp_a_significand_f16_0.tail(1).head(1) & fp_a_significand_f16_0.tail(2).orR
val fp_a_is_snan_f16_1 = Ea_f16_1.andR & !fp_a_significand_f16_1.tail(1).head(1) & fp_a_significand_f16_1.tail(2).orR
val fp_a_is_snan_f16_2 = Ea_f16_2.andR & !fp_a_significand_f16_2.tail(1).head(1) & fp_a_significand_f16_2.tail(2).orR
val fp_a_is_snan_f16_3 = Ea_f16_3.andR & !fp_a_significand_f16_3.tail(1).head(1) & fp_a_significand_f16_3.tail(2).orR
val fp_b_is_snan_f64 = Mux(io.res_widening & is_fp64,widen_Eb_f32_0.andR,Eb_f64.andR ) & !fp_b_significand_f64.tail(1).head(1) & fp_b_significand_f64.tail(2).orR
val fp_b_is_snan_f32_0 = Mux(io.res_widening & is_fp32,widen_Eb_f16_0.andR,Eb_f32_0.andR) & !fp_b_significand_f32_0.tail(1).head(1) & fp_b_significand_f32_0.tail(2).orR
val fp_b_is_snan_f32_1 = Mux(io.res_widening & is_fp32,widen_Eb_f16_1.andR,Eb_f32_1.andR) & !fp_b_significand_f32_1.tail(1).head(1) & fp_b_significand_f32_1.tail(2).orR
val fp_b_is_snan_f16_0 = Eb_f16_0.andR & !fp_b_significand_f16_0.tail(1).head(1) & fp_b_significand_f16_0.tail(2).orR
val fp_b_is_snan_f16_1 = Eb_f16_1.andR & !fp_b_significand_f16_1.tail(1).head(1) & fp_b_significand_f16_1.tail(2).orR
val fp_b_is_snan_f16_2 = Eb_f16_2.andR & !fp_b_significand_f16_2.tail(1).head(1) & fp_b_significand_f16_2.tail(2).orR
val fp_b_is_snan_f16_3 = Eb_f16_3.andR & !fp_b_significand_f16_3.tail(1).head(1) & fp_b_significand_f16_3.tail(2).orR
val fp_c_is_snan_f64 = Ec_f64.andR & !fp_c_significand_f64.tail(1).head(1) & fp_c_significand_f64.tail(2).orR
val fp_c_is_snan_f32_0 = Ec_f32_0.andR & !fp_c_significand_f32_0.tail(1).head(1) & fp_c_significand_f32_0.tail(2).orR
val fp_c_is_snan_f32_1 = Ec_f32_1.andR & !fp_c_significand_f32_1.tail(1).head(1) & fp_c_significand_f32_1.tail(2).orR
val fp_c_is_snan_f16_0 = Ec_f16_0.andR & !fp_c_significand_f16_0.tail(1).head(1) & fp_c_significand_f16_0.tail(2).orR
val fp_c_is_snan_f16_1 = Ec_f16_1.andR & !fp_c_significand_f16_1.tail(1).head(1) & fp_c_significand_f16_1.tail(2).orR
val fp_c_is_snan_f16_2 = Ec_f16_2.andR & !fp_c_significand_f16_2.tail(1).head(1) & fp_c_significand_f16_2.tail(2).orR
val fp_c_is_snan_f16_3 = Ec_f16_3.andR & !fp_c_significand_f16_3.tail(1).head(1) & fp_c_significand_f16_3.tail(2).orR
val has_nan_f64 = fp_a_is_nan_f64 | fp_b_is_nan_f64 | fp_c_is_nan_f64
val has_nan_f32_0 = fp_a_is_nan_f32_0 | fp_b_is_nan_f32_0 | fp_c_is_nan_f32_0
val has_nan_f32_1 = fp_a_is_nan_f32_1 | fp_b_is_nan_f32_1 | fp_c_is_nan_f32_1
Expand Down
16 changes: 8 additions & 8 deletions src/main/scala/yunsuan/vector/vfsqrt/fpsqrt_vector_r16.scala
Original file line number Diff line number Diff line change
Expand Up @@ -598,14 +598,14 @@ class fpsqrt_vector_r16(
op_is_inf_1 := op_exp_is_max_1 & op_frac_is_zero_1
op_is_inf_2 := op_exp_is_max_2 & op_frac_is_zero_2
op_is_inf_3 := op_exp_is_max_3 & op_frac_is_zero_3
op_is_qnan_0 := op_exp_is_max_0 & (Mux((fp_format_i === 0.U(2.W)), op_i(57), Mux((fp_format_i === 1.U(2.W)), op_i(54), op_i(51))))
op_is_qnan_1 := op_exp_is_max_1 & (Mux((fp_format_i === 0.U(2.W)), op_i(25), op_i(22)))
op_is_qnan_2 := op_exp_is_max_2 & op_i(41)
op_is_qnan_3 := op_exp_is_max_3 & op_i(9)
op_is_snan_0 := fp_aIsFpCanonicalNAN | op_exp_is_max_0 & ~op_frac_is_zero_0 & (Mux((fp_format_i === 0.U(2.W)), ~op_i(57), Mux((fp_format_i === 1.U(2.W)), ~op_i(54), ~op_i(51))))
op_is_snan_1 := fp_aIsFpCanonicalNAN | op_exp_is_max_1 & ~op_frac_is_zero_1 & (Mux((fp_format_i === 0.U(2.W)), ~op_i(25), ~op_i(22)))
op_is_snan_2 := fp_aIsFpCanonicalNAN | op_exp_is_max_2 & ~op_frac_is_zero_2 & ~op_i(41)
op_is_snan_3 := fp_aIsFpCanonicalNAN | op_exp_is_max_3 & ~op_frac_is_zero_3 & ~op_i(9)
op_is_qnan_0 := fp_aIsFpCanonicalNAN | op_exp_is_max_0 & (Mux((fp_format_i === 0.U(2.W)), op_i(57), Mux((fp_format_i === 1.U(2.W)), op_i(54), op_i(51))))
op_is_qnan_1 := fp_aIsFpCanonicalNAN | op_exp_is_max_1 & (Mux((fp_format_i === 0.U(2.W)), op_i(25), op_i(22)))
op_is_qnan_2 := fp_aIsFpCanonicalNAN | op_exp_is_max_2 & op_i(41)
op_is_qnan_3 := fp_aIsFpCanonicalNAN | op_exp_is_max_3 & op_i(9)
op_is_snan_0 := op_exp_is_max_0 & ~op_frac_is_zero_0 & (Mux((fp_format_i === 0.U(2.W)), ~op_i(57), Mux((fp_format_i === 1.U(2.W)), ~op_i(54), ~op_i(51))))
op_is_snan_1 := op_exp_is_max_1 & ~op_frac_is_zero_1 & (Mux((fp_format_i === 0.U(2.W)), ~op_i(25), ~op_i(22)))
op_is_snan_2 := op_exp_is_max_2 & ~op_frac_is_zero_2 & ~op_i(41)
op_is_snan_3 := op_exp_is_max_3 & ~op_frac_is_zero_3 & ~op_i(9)
op_is_nan_0 := (op_is_qnan_0 | op_is_snan_0)
op_is_nan_1 := (op_is_qnan_1 | op_is_snan_1)
op_is_nan_2 := (op_is_qnan_2 | op_is_snan_2)
Expand Down

0 comments on commit 4c33741

Please sign in to comment.