Skip to content

Releases: IntelLabs/simics-plus-rtl

Initial Release

28 Mar 22:12
@adavare adavare
v0.1
026b372
This commit was created on GitHub.com and signed with GitHub’s verified signature.
GPG key ID: B5690EEEBB952194
Learn about vigilant mode.
Compare
Choose a tag to compare
Initial Release Latest
Latest

This repository contains collateral for a Chisel-based RTL accelerator which is connected to a functional PCI bus using Simics. This accelerator carries out a simple operation: CRC32 calculation on the input bytes. User software running above an OS on the CPU can leverage the PCI accelerator for CRC32 computation.

The following 3 ingredients are located within this repository:

  1. Chisel source code and associated C++ harness.
  2. Simics device/component and unit tests.
  3. Target test code.
Assets 2
Loading