Implement COP1

README.md

@@ -126,9 +126,10 @@ See this crate at <https://crates.io/crates/rabbitizer>.
   - <http://www.raphnet.net/electronique/psx_adaptor/Playstation.txt>
 
 - R4000 ALLEGREX:
+  - ALLEGREX-Instruction_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/11356332/ALLEGREX-Instruction_Manual-English.pdf>
+  - FPU-Instruction_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/14950191/FPU-Instruction_Manual-English.pdf>
   - VFPU-Instruction_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/11356335/VFPU-Instruction_Manual-English.pdf>
   - VFPU-Users_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/11356333/VFPU-Users_Manual-English.pdf>
-  - ALLEGREX-Instruction_Manual-English <https://github.com/Decompollaborate/rabbitizer/files/11356332/ALLEGREX-Instruction_Manual-English.pdf>
   - yet another PlayStationPortable Documentation <http://hitmen.c02.at/files/yapspd/psp_doc/frames.html>
     - Chapter "4.8  Allegrex Instructions" <http://hitmen.c02.at/files/yapspd/psp_doc/chap4.html#sec4.8>
   - GNU binutils: <https://github.com/bminor/binutils-gdb/compare/011365b...a0176d8>

include/instructions/RabbitizerInstructionR4000Allegrex.h

@@ -64,6 +64,10 @@ NON_NULL(1)
 void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1(RabbitizerInstruction *self);
 NON_NULL(1)
 void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_BC1(RabbitizerInstruction *self);
+NON_NULL(1)
+void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuS(RabbitizerInstruction *self);
+NON_NULL(1)
+void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuW(RabbitizerInstruction *self);
 
 NON_NULL(1)
 void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2(RabbitizerInstruction *self);

src/instructions/RabbitizerInstruction/RabbitizerInstruction_ProcessUniqueId.c

@@ -166,6 +166,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor0_BC0(RabbitizerInstructio
     switch (fmt) {
 #include "tables/instr_id/cpu/cpu_cop0_bc0.inc"
     }
+
+    self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
 }
 
 void RabbitizerInstruction_processUniqueId_Coprocessor0_Tlb(RabbitizerInstruction *self) {
@@ -177,6 +179,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor0_Tlb(RabbitizerInstructio
     switch (function) {
 #include "tables/instr_id/cpu/cpu_cop0_tlb.inc"
     }
+
+    self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
 }
 
 void RabbitizerInstruction_processUniqueId_Coprocessor0(RabbitizerInstruction *self) {
@@ -210,6 +214,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_BC1(RabbitizerInstructio
     switch (fmt) {
 #include "tables/instr_id/cpu/cpu_cop1_bc1.inc"
     }
+
+    self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
 }
 
 void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuS(RabbitizerInstruction *self) {
@@ -221,6 +227,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuS(RabbitizerInstructi
     switch (function) {
 #include "tables/instr_id/cpu/cpu_cop1_fpu_s.inc"
     }
+
+    self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
 }
 
 void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuD(RabbitizerInstruction *self) {
@@ -232,6 +240,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuD(RabbitizerInstructi
     switch (function) {
 #include "tables/instr_id/cpu/cpu_cop1_fpu_d.inc"
     }
+
+    self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
 }
 
 void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuW(RabbitizerInstruction *self) {
@@ -243,6 +253,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuW(RabbitizerInstructi
     switch (function) {
 #include "tables/instr_id/cpu/cpu_cop1_fpu_w.inc"
     }
+
+    self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
 }
 
 void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuL(RabbitizerInstruction *self) {
@@ -254,6 +266,8 @@ void RabbitizerInstruction_processUniqueId_Coprocessor1_FpuL(RabbitizerInstructi
     switch (function) {
 #include "tables/instr_id/cpu/cpu_cop1_fpu_l.inc"
     }
+
+    self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
 }
 
 void RabbitizerInstruction_processUniqueId_Coprocessor1(RabbitizerInstruction *self) {

src/instructions/RabbitizerInstructionR4000Allegrex/RabbitizerInstructionR4000Allegrex_ProcessUniqueId.c

@@ -261,10 +261,18 @@ void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1(RabbitizerI
             break;
 
         case 0x10:
-        case 0x11:
+            RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuS(self);
+            fetchDescriptor = false;
+            break;
+
         case 0x14:
+            RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuW(self);
+            fetchDescriptor = false;
+            break;
+
+        case 0x11:
         case 0x15:
-            // ????
+            // Allegrex doesn't have D and L?
             break;
 
         default:
@@ -300,6 +308,59 @@ void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_BC1(Rabbiti
     }
 }
 
+void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuS(RabbitizerInstruction *self) {
+    uint32_t function = RAB_INSTR_GET_function(self);
+    bool fetchDescriptor = true;
+
+    self->_mandatorybits = RAB_INSTR_PACK_function(self->_mandatorybits, function);
+    self->instrIdType = RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUS;
+
+    switch (function) {
+#include "tables/instr_id/r4000allegrex/r4000allegrex_cop1_fpu_s.inc"
+
+        case 0x08:
+        case 0x09:
+        case 0x0A:
+        case 0x0B:
+        case 0x21:
+        case 0x25:
+            break;
+
+        default:
+            RabbitizerInstruction_processUniqueId_Coprocessor1_FpuS(self);
+            fetchDescriptor = false;
+            break;
+    }
+
+    if (fetchDescriptor) {
+        self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
+    }
+}
+
+void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor1_FpuW(RabbitizerInstruction *self) {
+    uint32_t function = RAB_INSTR_GET_function(self);
+    bool fetchDescriptor = true;
+
+    self->_mandatorybits = RAB_INSTR_PACK_function(self->_mandatorybits, function);
+    self->instrIdType = RAB_INSTR_ID_TYPE_R4000ALLEGREX_COP1_FPUW;
+
+    switch (function) {
+#include "tables/instr_id/r4000allegrex/r4000allegrex_cop1_fpu_w.inc"
+
+        case 0x21:
+            break;
+
+        default:
+            RabbitizerInstruction_processUniqueId_Coprocessor1_FpuW(self);
+            fetchDescriptor = false;
+            break;
+    }
+
+    if (fetchDescriptor) {
+        self->descriptor = &RabbitizerInstrDescriptor_Descriptors[self->uniqueId];
+    }
+}
+
 void RabbitizerInstructionR4000Allegrex_processUniqueId_Coprocessor2(RabbitizerInstruction *self) {
     uint32_t fmt = RAB_INSTR_GET_fmt(self);
     bool fetchDescriptor = true;

tables/tables/instr_id/RabbitizerInstrId_r4000allegrex.inc

@@ -26,6 +26,8 @@
 
     #include "r4000allegrex/r4000allegrex_cop1.inc"
     #include "r4000allegrex/r4000allegrex_cop1_bc1.inc"
+    #include "r4000allegrex/r4000allegrex_cop1_fpu_s.inc"
+    #include "r4000allegrex/r4000allegrex_cop1_fpu_w.inc"
 
     #include "r4000allegrex/r4000allegrex_cop2.inc"
     #include "r4000allegrex/r4000allegrex_cop2_bc2.inc"

tables/tables/instr_id/cpu/cpu_cop1.inc

@@ -11,8 +11,10 @@
  10 | *2    | *3    | ---   | ---   | *4    | *5    | ---   | ---   |
  11 | ---   | ---   | ---   | ---   | ---   | ---   | ---   | ---   |
  hi |-------|-------|-------|-------|-------|-------|-------|-------|
-     *1 = BC instructions, see BC1 list   *2 = S instr, see FPU S list
-     *3 = D instr, see FPU D list         *4 = W instr, see FPU W list
+     *1 = BC instructions, see BC1 list
+     *2 = S instr, see FPU S list
+     *3 = D instr, see FPU D list
+     *4 = W instr, see FPU W list
      *5 = L instr, see FPU L list
 */
 

tables/tables/instr_id/cpu/cpu_cop1_fpu_d.inc

@@ -3,7 +3,7 @@
 
 /*
     31----------26-25--------21 -----------------------------------------5----------0
-    |   = COP1    |   = S     |                                         | function  |
+    |   = COP1    |   = D     |                                         | function  |
     -------6------------5-----------------------------------------------------6------
     |---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
 000 | ADD.D   | SUB.D   | MUL.D   | DIV.D   | SQRT.D  | ABS.D   | MOV.D   | NEG.D   |

tables/tables/instr_id/cpu/cpu_cop1_fpu_l.inc

@@ -3,7 +3,7 @@
 
 /*
     31----------26-25--------21 -----------------------------------------5----------0
-    |   = COP1    |   = S     |                                         | function  |
+    |   = COP1    |   = L     |                                         | function  |
     -------6------------5-----------------------------------------------------6------
     |---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
 000 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |

tables/tables/instr_id/cpu/cpu_cop1_fpu_w.inc

@@ -3,7 +3,7 @@
 
 /*
     31----------26-25--------21 -----------------------------------------5----------0
-    |   = COP1    |   = S     |                                         | function  |
+    |   = COP1    |   = W     |                                         | function  |
     -------6------------5-----------------------------------------------------6------
     |---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
 000 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |

tables/tables/instr_id/r4000allegrex/r4000allegrex_cop1.inc

@@ -8,10 +8,12 @@
     |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
  00 | MFC1  | ---   | CFC1  | MFHC1 | MTC1  | ---   | CTC1  | MTHC1 |
  01 | *1    | ---   | ---   | ---   | ---   | ---   | ---   | ---   |
- 10 | ---   | ---   | ---   | ---   | ---   | ---   | ---   | ---   |
+ 10 | *2    | ---   | ---   | ---   | *3    | ---   | ---   | ---   |
  11 | ---   | ---   | ---   | ---   | ---   | ---   | ---   | ---   |
  hi |-------|-------|-------|-------|-------|-------|-------|-------|
-       *1=BC See BC1 list
+     *1 = BC See BC1 list
+     *2 = S instr, see FPU S list
+     *3 = W instr, see FPU W list
 */
 
 /*

tables/tables/instr_id/r4000allegrex/r4000allegrex_cop1_fpu_s.inc

@@ -0,0 +1,20 @@
+/* SPDX-FileCopyrightText: © 2024 Decompollaborate */
+/* SPDX-License-Identifier: MIT */
+
+/*
+    31----------26-25--------21 -----------------------------------------5----------0
+    |   = COP1    |   = S     |                                         | function  |
+    -------6------------5-----------------------------------------------------6------
+    |---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
+000 | ADD.S   | SUB.S   | MUL.S   | DIV.S   | SQRT.S  | ABS.S   | MOV.S   | NEG.S   |
+001 | ---     | ---     | ---     | ---     |ROUND.W.S|TRUNC.W.S| CEIL.W.S|FLOOR.W.S|
+010 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+011 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+100 | ---     | ---     | ---     | ---     | CVT.W.S | ---     | ---     | ---     |
+101 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+110 | C.F.S   | C.UN.S  | C.EQ.S  | C.UEQ.S | C.OLT.S | C.ULT.S | C.OLE.S | C.ULE.S |
+111 | C.SF.S  | C.NGLE.S| C.SEQ.S | C.NGL.S | C.LT.S  | C.NGE.S | C.LE.S  | C.NGT.S |
+ hi |---------|---------|---------|---------|---------|---------|---------|---------|
+*/
+
+    // The other instructions are implemented using the main CPU table

tables/tables/instr_id/r4000allegrex/r4000allegrex_cop1_fpu_w.inc

@@ -0,0 +1,20 @@
+/* SPDX-FileCopyrightText: © 2022-2024 Decompollaborate */
+/* SPDX-License-Identifier: MIT */
+
+/*
+    31----------26-25--------21 -----------------------------------------5----------0
+    |   = COP1    |   = W     |                                         | function  |
+    -------6------------5-----------------------------------------------------6------
+    |---000---|---001---|---010---|---011---|---100---|---101---|---110---|---111---| lo
+000 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+001 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+010 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+011 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+100 | CVT.S.W | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+101 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+110 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+111 | ---     | ---     | ---     | ---     | ---     | ---     | ---     | ---     |
+ hi |---------|---------|---------|---------|---------|---------|---------|---------|
+*/
+
+    // The other instructions are implemented using the main CPU table

tables/tables/instr_id_types/InstrIdType_r4000allegrex.inc

@@ -22,10 +22,8 @@
 
     RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1)
     RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1_BC1)
-    //RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1_FPUS)
-    //RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1_FPUD)
-    //RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1_FPUW)
-    //RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1_FPUL)
+    RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1_FPUS)
+    RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP1_FPUW)
 
     RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP2)
     RABBITIZER_DEF_INSTR_ID_TYPE(R4000ALLEGREX, COP2_BC2)

tests/c/instruction_checks/r4000allegrex_disasm.c

@@ -95,6 +95,20 @@ const TestEntry test_entries[] = {
     TEST_ENTRY_C(0x70000024, NULL, "mfie        $zero"),
     TEST_ENTRY_C(0x70000026, NULL, "mtie        $zero"),
     TEST_ENTRY_C(0x70040026, NULL, "mtie        $a0"),
+
+    /* Allegrex removed 64 bits FPU instructions */
+    TEST_ENTRY_C(0x468020A1, NULL, ".word       0x468020A1                   # INVALID     $s4, $zero, 0x20A1 # 00000000 <InstrIdType: R4000ALLEGREX_COP1_FPUW>"),
+    TEST_ENTRY_C(0x46002088, NULL, ".word       0x46002088                   # INVALID     $s0, $zero, 0x2088 # 00000000 <InstrIdType: R4000ALLEGREX_COP1_FPUS>"),
+    TEST_ENTRY_C(0x46002089, NULL, ".word       0x46002089                   # INVALID     $s0, $zero, 0x2089 # 00000000 <InstrIdType: R4000ALLEGREX_COP1_FPUS>"),
+    TEST_ENTRY_C(0x4600208A, NULL, ".word       0x4600208A                   # INVALID     $s0, $zero, 0x208A # 00000000 <InstrIdType: R4000ALLEGREX_COP1_FPUS>"),
+    TEST_ENTRY_C(0x4600208B, NULL, ".word       0x4600208B                   # INVALID     $s0, $zero, 0x208B # 00000000 <InstrIdType: R4000ALLEGREX_COP1_FPUS>"),
+    TEST_ENTRY_C(0x460020A1, NULL, ".word       0x460020A1                   # INVALID     $s0, $zero, 0x20A1 # 00000000 <InstrIdType: R4000ALLEGREX_COP1_FPUS>"),
+    TEST_ENTRY_C(0x460020A5, NULL, ".word       0x460020A5                   # INVALID     $s0, $zero, 0x20A5 # 00000000 <InstrIdType: R4000ALLEGREX_COP1_FPUS>"),
+
+    TEST_ENTRY_C(0x46002085, NULL, "abs.s       $f2, $f4"),
+    TEST_ENTRY_C(0x46042080, NULL, "add.s       $f2, $f4, $f4"),
+    TEST_ENTRY_C(0x45000008, NULL, "bc1f        . + 4 + (0x8 << 2)"),
+    TEST_ENTRY_C(0x46100030, NULL, "c.f.s       $f0, $f16"),
 };
 
 size_t test_entries_len = ARRAY_COUNT(test_entries);