Merge pull request #51 from CESM-Development/fischer/testlist_compset…

…name

Updates to testlist_allactive

testlist_allactive.xml

@@ -56,7 +56,7 @@
       <option name="wallclock"> 06:00 </option>
     </options>
   </test>
-  <test name="IRT" grid="f19_g17" compset="B1850C4L45BGCRBPRPWs" testmods="allactive/defaultio">
+  <test name="IRT" grid="f19_g17" compset="B1850Ws" testmods="allactive/defaultio">
     <machines>
       <machine name="bluewaters" compiler="pgi" category="prebeta"/>
     </machines>
@@ -160,7 +160,7 @@
       <option name="wallclock"> 00:30 </option>
     </options>
   </test>
-  <test name="ERS_Ld7" grid="f09_g17" compset="BHISTC5L45BGCR" testmods="allactive/defaultio">
+  <test name="ERS_Ld7" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
     <machines>
       <machine name="bluewaters" compiler="pgi" category="prebeta"/>
     </machines>
@@ -229,14 +229,6 @@
       <option name="wallclock"> 00:30 </option>
     </options>
   </test>
-  <!-- <test name="PET" grid="f19_g17" compset="B1850C5L40SPRWs" testmods="allactive/defaultio"> -->
-  <!--   <machines> -->
-  <!--     <machine name="bluewaters" compiler="pgi" category="prebeta"/> -->
-  <!--   </machines> -->
-  <!--   <options> -->
-  <!--     <option name="wallclock"> 00:30 </option> -->
-  <!--   </options> -->
-  <!-- </test> -->
   <test name="PFS" grid="f09_g17" compset="B1850" testmods="allactive/default">
     <machines>
       <machine name="bluewaters" compiler="pgi" category="prebeta"/>
@@ -269,10 +261,6 @@
       <machine name="cheyenne" compiler="intel" category="aux_perf"/>
     </machines>
   </test>
-
-
-
-
   <test name="PFS" grid="ne30_g17" compset="B1850" testmods="allactive/default">
     <machines>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
@@ -333,14 +321,6 @@
       <option name="wallclock"> 00:45 </option>
     </options>
   </test>
-  <!-- <test name="SMS_Ld5" grid="f09_g17" compset="BRCP85C4L40CNRBPRP" testmods="allactive/defaultio"> -->
-  <!--   <machines> -->
-  <!--     <machine name="edison" compiler="intel" category="prebeta"/> -->
-  <!--   </machines> -->
-  <!--   <options> -->
-  <!--     <option name="wallclock"> 00:30 </option> -->
-  <!--   </options> -->
-  <!-- </test> -->
   <test name="SMS_Ld5" grid="f09_g17_gl4" compset="J1850G" testmods="allactive/cism/test_coupling">
     <machines>
       <machine name="cheyenne" compiler="gnu" category="prebeta"/>