Merge pull request #42 from CESM-Development/fischer/compset_upate

Moving some compsets from CAM50 to CAM60.
CESM-Development · Dec 20, 2017 · 38caa47 · 38caa47
2 parents aa1574d + fdce6b7
commit 38caa47
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Showing 2 changed files with 12 additions and 12 deletions.
diff --git a/config_compsets.xml b/config_compsets.xml
@@ -165,8 +165,8 @@
   </compset>
 
   <compset>
-    <alias>B1850C5L45BGCR</alias>
-    <lname>1850_CAM50_CLM45%BGC_CICE_POP2_RTM_SGLC_SWAV</lname>
+    <alias>B1850L45BGCR</alias>
+    <lname>1850_CAM60_CLM45%BGC_CICE_POP2_RTM_SGLC_SWAV</lname>
   </compset>
 
 <!--  <compset> -->
@@ -200,8 +200,8 @@
 <!--  </compset> -->
 
   <compset>
-    <alias>BRCP85C5L45BGCR</alias>
-    <lname>RCP8_CAM50_CLM45%BGC_CICE_POP2_RTM_SGLC_SWAV</lname>
+    <alias>BRCP85L45BGCR</alias>
+    <lname>RCP8_CAM60_CLM45%BGC_CICE_POP2_RTM_SGLC_SWAV</lname>
   </compset>
 
   <compset>
@@ -227,8 +227,8 @@
   </compset>
 
   <compset>
-    <alias>B1850C5L45BGCRBPRP</alias>
-    <lname>1850_CAM50_CLM45%BGC_CICE_POP2%ECO_RTM_SGLC_SWAV_BGC%BPRP</lname>
+    <alias>B1850L45BGCRBPRP</alias>
+    <lname>1850_CAM60_CLM45%BGC_CICE_POP2%ECO_RTM_SGLC_SWAV_BGC%BPRP</lname>
   </compset>
 
 <!--  <compset> -->
@@ -274,8 +274,8 @@
   </compset>
 
   <compset>
-    <alias>E1850C5L45TEST</alias>
-    <lname>1850_CAM50_CLM45%SP_CICE_DOCN%SOM_MOSART_SGLC_SWAV_TEST</lname>
+    <alias>E1850L45TEST</alias>
+    <lname>1850_CAM60_CLM45%SP_CICE_DOCN%SOM_MOSART_SGLC_SWAV_TEST</lname>
   </compset>
 
   <!-- All active except data atmosphere

diff --git a/testlist_allactive.xml b/testlist_allactive.xml
@@ -82,7 +82,7 @@
       <option name="wallclock"> 00:25 </option>
     </options>
   </test>
-  <test name="IRT" grid="f09_g17" compset="BRCP85C5L45BGCR" testmods="allactive/defaultio">
+  <test name="IRT" grid="f09_g17" compset="BRCP85L45BGCR" testmods="allactive/defaultio">
     <machines>
       <machine name="cheyenne" compiler="intel" category="prebeta"/>
     </machines>
@@ -125,15 +125,15 @@
       <option name="wallclock"> 01:00 </option>
     </options>
   </test>
-  <test name="IRT_Ld7" grid="T31_g37" compset="B1850C5L45BGCR" testmods="allactive/defaultio">
+  <test name="IRT_Ld7" grid="T31_g37" compset="B1850L45BGCR" testmods="allactive/defaultio">
     <machines>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
     </machines>
     <options>
       <option name="wallclock"> 01:00 </option>
     </options>
   </test>
-  <test name="ERS_Ld5" grid="f19_g17" compset="E1850C5L45TEST" testmods="cice/default">
+  <test name="ERS_Ld5" grid="f19_g17" compset="E1850L45TEST" testmods="cice/default">
     <machines>
       <machine name="cheyenne" compiler="intel" category="prebeta"/>
     </machines>
@@ -186,7 +186,7 @@
       <option name="wallclock"> 02:00 </option>
     </options>
   </test>
-  <test name="ERS_Ld7" grid="f09_g17" compset="BRCP85C5L45BGCR" testmods="allactive/defaultio">
+  <test name="ERS_Ld7" grid="f09_g17" compset="BRCP85L45BGCR" testmods="allactive/defaultio">
     <machines>
       <machine name="edison" compiler="intel" category="prebeta"/>
     </machines>