Design & Comparative Analysis of Novel 8T and 6T SRAM Cell Using 16nm Technology. This project focuses on the design and analysis of memory blocks, specifically Static Random Access Memory (SRAM) cells, a critical component in modern computing systems. Unlike volatile memories such as DRAM, SRAMs are preferred for their faster access times, reduced power consumption, and reliability due to the absence of periodic refreshing.
Overview The study compares 6T and Novel 8T SRAM cells, evaluating their performance based on key parameters:
Static Noise Margin (SNM): Measures robustness against noise. Power Dissipation: Energy consumed during operation. Area Consumption: Physical size of the cell layout. Delay: Time taken to access or write data. Key Results Leakage Current: Maximum in 8T: 169.9522 pA Minimum in 6T: 66.1483 pA Static Noise Margin (SNM): 6T: 0.3044 V 8T: 0.1677 V Power Dissipation: Maximum (6T): 665.59 nW Minimum (8T): 74.685 nW Tools & Methodology Simulation: DC and transient analysis using LTSpice. Layout Design & Verification: DRC and LVS checks performed using Cadence Virtuoso Tool Suite. This comparative study highlights the trade-offs between traditional 6T and the proposed Novel 8T SRAM cells, providing insights into their suitability for different applications based on power, noise resilience, and performance.