masm: complete macro assembly for ALU128

AluVM · Nov 4, 2024 · 015d437 · 015d437
1 parent 04a8dbb
commit 015d437
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Showing 9 changed files with 420 additions and 18 deletions.
diff --git a/src/core/microcode/base.rs b/src/core/microcode/base.rs
@@ -141,7 +141,7 @@ impl From<u8> for RegA {
     }
 }
 
-#[derive(Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Debug, Display)]
+#[derive(Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Debug, Display, From)]
 #[display(inner)]
 pub struct IdxA(Idx32);
 
@@ -156,7 +156,7 @@ impl From<u5> for IdxA {
     fn from(idx: u5) -> Self { Self(Idx32::from(idx)) }
 }
 
-#[derive(Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Debug, Display)]
+#[derive(Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Debug, Display, From)]
 #[display(inner)]
 pub struct IdxAl(Idx16);
 

diff --git a/src/core/mod.rs b/src/core/mod.rs
@@ -32,5 +32,4 @@ pub use self::core::{Core, CoreConfig, CALL_STACK_SIZE_MAX};
 #[cfg(feature = "GFA")]
 pub use self::microcode::gfa;
 pub use self::microcode::{IdxA, IdxAl, Reg, RegA, A};
-pub(self) use self::regs::{Idx16, Idx32};
-pub use self::regs::{Site, SiteId, Status};
+pub use self::regs::{Idx16, Idx32, Site, SiteId, Status};
diff --git a/src/core/regs.rs b/src/core/regs.rs
@@ -62,7 +62,7 @@ impl<Id: SiteId> Display for Site<Id> {
 #[allow(dead_code)]
 #[derive(Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Debug, Display)]
 #[repr(u8)]
-pub(super) enum Idx16 {
+pub enum Idx16 {
     #[display(":1")]
     L1 = 0,
     #[display(":2")]
@@ -141,7 +141,7 @@ impl From<u4> for Idx16 {
 
 #[derive(Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Debug, Display)]
 #[repr(u8)]
-pub(super) enum Idx32 {
+pub enum Idx32 {
     #[display(":1")]
     L1 = 0,
     #[display(":2")]

diff --git a/src/isa/alu/bytecode.rs b/src/isa/alu/bytecode.rs
@@ -132,8 +132,8 @@ impl<Id: SiteId> Bytecode<Id> for CtrlInstr<Id> {
             CtrlInstr::FailCk => Self::FAIL,
             CtrlInstr::RsetCk => Self::RSET,
             CtrlInstr::Jmp { .. } => Self::JMP,
-            CtrlInstr::JifCo { .. } => Self::JIFNE,
-            CtrlInstr::JifCk { .. } => Self::JIFAIL,
+            CtrlInstr::JiNe { .. } => Self::JIFNE,
+            CtrlInstr::JiFail { .. } => Self::JIFAIL,
             CtrlInstr::Sh { .. } => Self::SH,
             CtrlInstr::ShNe { .. } => Self::SHNE,
             CtrlInstr::ShFail { .. } => Self::SHFAIL,
@@ -156,7 +156,7 @@ impl<Id: SiteId> Bytecode<Id> for CtrlInstr<Id> {
             | CtrlInstr::Ret
             | CtrlInstr::Stop => {}
 
-            CtrlInstr::Jmp { pos } | CtrlInstr::JifCo { pos } | CtrlInstr::JifCk { pos } | CtrlInstr::Fn { pos } => {
+            CtrlInstr::Jmp { pos } | CtrlInstr::JiNe { pos } | CtrlInstr::JiFail { pos } | CtrlInstr::Fn { pos } => {
                 writer.write_fixed(pos.to_le_bytes())?
             }
             CtrlInstr::Sh { shift } | CtrlInstr::ShNe { shift } | CtrlInstr::ShFail { shift } => {
@@ -188,10 +188,10 @@ impl<Id: SiteId> Bytecode<Id> for CtrlInstr<Id> {
             Self::JMP => CtrlInstr::Jmp {
                 pos: reader.read_fixed(u16::from_le_bytes)?,
             },
-            Self::JIFNE => CtrlInstr::JifCo {
+            Self::JIFNE => CtrlInstr::JiNe {
                 pos: reader.read_fixed(u16::from_le_bytes)?,
             },
-            Self::JIFAIL => CtrlInstr::JifCk {
+            Self::JIFAIL => CtrlInstr::JiFail {
                 pos: reader.read_fixed(u16::from_le_bytes)?,
             },
             Self::FN => CtrlInstr::Fn {

diff --git a/src/isa/alu/exec.rs b/src/isa/alu/exec.rs
@@ -113,7 +113,7 @@ impl<Id: SiteId> Instruction<Id> for CtrlInstr<Id> {
     fn op_data_bytes(&self) -> u16 {
         match self {
             CtrlInstr::Nop | CtrlInstr::Chk | CtrlInstr::NotCo | CtrlInstr::FailCk | CtrlInstr::RsetCk => 0,
-            CtrlInstr::Jmp { .. } | CtrlInstr::JifCo { .. } | CtrlInstr::JifCk { .. } => 2,
+            CtrlInstr::Jmp { .. } | CtrlInstr::JiNe { .. } | CtrlInstr::JiFail { .. } => 2,
             CtrlInstr::Sh { .. } | CtrlInstr::ShNe { .. } | CtrlInstr::ShFail { .. } => 1,
             CtrlInstr::Exec { .. } => 0,
             CtrlInstr::Fn { .. } => 2,
@@ -125,7 +125,7 @@ impl<Id: SiteId> Instruction<Id> for CtrlInstr<Id> {
     fn ext_data_bytes(&self) -> u16 {
         match self {
             CtrlInstr::Nop | CtrlInstr::Chk | CtrlInstr::NotCo | CtrlInstr::FailCk | CtrlInstr::RsetCk => 0,
-            CtrlInstr::Jmp { .. } | CtrlInstr::JifCo { .. } | CtrlInstr::JifCk { .. } => 0,
+            CtrlInstr::Jmp { .. } | CtrlInstr::JiNe { .. } | CtrlInstr::JiFail { .. } => 0,
             CtrlInstr::Sh { .. } | CtrlInstr::ShNe { .. } | CtrlInstr::ShFail { .. } => 0,
             CtrlInstr::Exec { .. } => 32,
             CtrlInstr::Fn { .. } => 0,
@@ -160,12 +160,12 @@ impl<Id: SiteId> Instruction<Id> for CtrlInstr<Id> {
             }
             CtrlInstr::NotCo => core.set_co(!core.co()),
             CtrlInstr::Jmp { pos } => return ExecStep::Jump(pos),
-            CtrlInstr::JifCo { pos } => {
+            CtrlInstr::JiNe { pos } => {
                 if core.co() {
                     return ExecStep::Jump(pos);
                 }
             }
-            CtrlInstr::JifCk { pos } => {
+            CtrlInstr::JiFail { pos } => {
                 if core.ck() == Status::Fail {
                     return ExecStep::Jump(pos);
                 }

diff --git a/src/isa/alu/instr.rs b/src/isa/alu/instr.rs
@@ -74,11 +74,11 @@ pub enum CtrlInstr<Id: SiteId> {
 
     /// Jump to location if `CO` is true.
     #[display("jif     CO, {pos:04X}#h")]
-    JifCo { pos: u16 },
+    JiNe { pos: u16 },
 
     /// Jump to location if `ck` is in a failed state.
     #[display("jif     CK, {pos:04X}#h")]
-    JifCk { pos: u16 },
+    JiFail { pos: u16 },
 
     /// Relative jump.
     #[display("jmp     {shift:+03X}#h")]