From 62e6c3d626999acebf0419c7f5b02100661f60e3 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Fri, 19 Apr 2024 14:48:00 +0300 Subject: [PATCH 1/5] VP(HPC-CLINT): pick another timer base & remove typo --- vp/devel/hpc.repl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vp/devel/hpc.repl b/vp/devel/hpc.repl index 38d01b44..2758aeb3 100644 --- a/vp/devel/hpc.repl +++ b/vp/devel/hpc.repl @@ -22,7 +22,7 @@ sdram: Memory.MappedMemory @ sysbus 0x10000000 size: 0x60000000 /* - * CLINT <> [^1] + * CLINT [^1] * * [IP](https://gitlab.tuni.fi/soc-hub/common/hw/cva6/-/tree/master/corev_apu/clint) * [Specification](https://github.com/pulp-platform/clint) (unconfirmed) @@ -33,7 +33,7 @@ clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x60000 [4, 5] -> cpu_hpc2@[3, 7] // msoft, mtimer [6, 7] -> cpu_hpc3@[3, 7] // msoft, mtimer numberOfTargets: 4 - frequency: 100000 // we guess board reference frequency + frequency: 32768 // we guess the usual RTC freq. of 32.768 kHz /* * PLIC [^1] From 7fdc6c32dcd493ec206ae2089563957cc093e161 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Fri, 19 Apr 2024 15:24:57 +0300 Subject: [PATCH 2/5] BSP: split hpc/sysctrl-rt into hpc/sysctrl + *-rt --- examples/headsail-bsp/Cargo.toml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/examples/headsail-bsp/Cargo.toml b/examples/headsail-bsp/Cargo.toml index 48c1b2fb..d2026869 100644 --- a/examples/headsail-bsp/Cargo.toml +++ b/examples/headsail-bsp/Cargo.toml @@ -6,13 +6,16 @@ edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [features] -hpc-rt = ["rt"] +hpc-rt = ["hpc", "rt"] sysctrl-rt = [ + "sysctrl", "rt", "riscv-rt/single-hart", "riscv/critical-section-single-hart", ] panic-uart = [] +hpc = [] +sysctrl = [] # This is generated by the above options, don't use directly rt = ["dep:riscv-rt", "dep:riscv"] From 5175720097ccd4aea8ded610fa098d4b80f50cfb Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Fri, 19 Apr 2024 15:28:37 +0300 Subject: [PATCH 3/5] BSP: add drivers for CLINT, PLIC --- examples/headsail-bsp/Cargo.toml | 4 +- examples/headsail-bsp/src/hpc/interrupt.rs | 71 ++++++++++++++++++++++ examples/headsail-bsp/src/hpc/mod.rs | 35 +++++++++++ examples/headsail-bsp/src/lib.rs | 4 ++ 4 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 examples/headsail-bsp/src/hpc/interrupt.rs create mode 100644 examples/headsail-bsp/src/hpc/mod.rs diff --git a/examples/headsail-bsp/Cargo.toml b/examples/headsail-bsp/Cargo.toml index d2026869..91b37b48 100644 --- a/examples/headsail-bsp/Cargo.toml +++ b/examples/headsail-bsp/Cargo.toml @@ -6,7 +6,7 @@ edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [features] -hpc-rt = ["hpc", "rt"] +hpc-rt = ["hpc", "rt", "dep:riscv-peripheral", "dep:riscv-pac"] sysctrl-rt = [ "sysctrl", "rt", @@ -24,6 +24,8 @@ rt = ["dep:riscv-rt", "dep:riscv"] ufmt = "0.2.0" riscv-rt = { version = "0.12.2", optional = true } riscv = { version = "0.11.1", optional = true } +riscv-peripheral = { version = "0.1.0", optional = true } +riscv-pac = { version = "0.1.1", optional = true } [[example]] name = "panic" diff --git a/examples/headsail-bsp/src/hpc/interrupt.rs b/examples/headsail-bsp/src/hpc/interrupt.rs new file mode 100644 index 00000000..14b93855 --- /dev/null +++ b/examples/headsail-bsp/src/hpc/interrupt.rs @@ -0,0 +1,71 @@ +use crate::HartId; +use riscv_pac::PriorityNumber; + +// HPC-SS specifies that priorities go up to 7 +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Priority { + P0 = 0, + P1 = 1, + P2 = 2, + P3 = 3, + P4 = 4, + P5 = 5, + P6 = 6, + P7 = 7, +} + +unsafe impl PriorityNumber for Priority { + const MAX_PRIORITY_NUMBER: u8 = 7; + + #[inline] + fn number(self) -> u8 { + self as _ + } + + #[inline] + fn from_number(number: u8) -> Result { + if number > Self::MAX_PRIORITY_NUMBER { + Err(number) + } else { + // SAFETY: valid priority number + Ok(unsafe { core::mem::transmute(number) }) + } + } +} + +riscv_peripheral::clint_codegen!( + base 0x60000, + freq 32_768, + mtimecmps [ + mtimecmp0 = (HartId::H0, "`H0`"), + mtimecmp1 = (HartId::H1, "`H1`"), + mtimecmp2 = (HartId::H2, "`H2`"), + mtimecmp3 = (HartId::H3, "`H3`") + ], + msips [ + msip0 = (HartId::H0, "`H0`"), + msip1 = (HartId::H1, "`H1`"), + msip2 = (HartId::H2, "`H2`"), + msip3 = (HartId::H3, "`H3`") + ], +); + +// ???: ASIC developer beware +// +// Some addresses were tightened to save space for Headsail's PLIC. That means that the ASIC will be +// different from the sim, and that this `riscv_peripheral` provided driver won't work as-is on +// ASIC, while it works perfectly well with the sim. +riscv_peripheral::plic_codegen!( + base 0x80000, + ctxs [ + ctx0 = (HartId::H0, "`H0M`"), + ctx1 = (HartId::H0, "`H0S`"), + ctx2 = (HartId::H1, "`H1M`"), + ctx3 = (HartId::H1, "`H1S`"), + ctx4 = (HartId::H2, "`H2M`"), + ctx5 = (HartId::H2, "`H2S`"), + ctx6 = (HartId::H3, "`H3M`"), + ctx7 = (HartId::H3, "`H3S`") + ], +); diff --git a/examples/headsail-bsp/src/hpc/mod.rs b/examples/headsail-bsp/src/hpc/mod.rs new file mode 100644 index 00000000..304f3ca5 --- /dev/null +++ b/examples/headsail-bsp/src/hpc/mod.rs @@ -0,0 +1,35 @@ +//! Abstractions that only exist on HPC + +pub mod interrupt; +pub use interrupt::*; + +use riscv_pac::HartIdNumber; + +/// HPC has 4 HARTs +#[repr(u16)] +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub enum HartId { + H0 = 0, + H1 = 1, + H2 = 2, + H3 = 3, +} + +unsafe impl HartIdNumber for HartId { + const MAX_HART_ID_NUMBER: u16 = 3; + + #[inline] + fn number(self) -> u16 { + self as _ + } + + #[inline] + fn from_number(number: u16) -> Result { + if number > Self::MAX_HART_ID_NUMBER { + Err(number) + } else { + // SAFETY: valid context number + Ok(unsafe { core::mem::transmute(number) }) + } + } +} diff --git a/examples/headsail-bsp/src/lib.rs b/examples/headsail-bsp/src/lib.rs index 0ad002bc..d33a8119 100644 --- a/examples/headsail-bsp/src/lib.rs +++ b/examples/headsail-bsp/src/lib.rs @@ -4,10 +4,14 @@ pub mod sprintln; pub mod uart; +#[cfg(feature = "hpc")] +pub use hpc::*; #[cfg(any(feature = "rt"))] pub use riscv_rt as rt; pub use ufmt; +#[cfg(feature = "hpc")] +mod hpc; mod mmap; #[cfg(any(feature = "panic-uart"))] mod ufmt_panic; From 32c07bc1b2946706d939e984de53ef3324419163 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Fri, 19 Apr 2024 15:29:02 +0300 Subject: [PATCH 4/5] Minor cfg format --- examples/headsail-bsp/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/headsail-bsp/src/lib.rs b/examples/headsail-bsp/src/lib.rs index d33a8119..8c36a0cc 100644 --- a/examples/headsail-bsp/src/lib.rs +++ b/examples/headsail-bsp/src/lib.rs @@ -6,7 +6,7 @@ pub mod uart; #[cfg(feature = "hpc")] pub use hpc::*; -#[cfg(any(feature = "rt"))] +#[cfg(feature = "rt")] pub use riscv_rt as rt; pub use ufmt; From 4124969a89d2dff91ff0554a35a846a122996212 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Fri, 19 Apr 2024 15:30:07 +0300 Subject: [PATCH 5/5] BSP: expose riscv at root --- examples/headsail-bsp/src/lib.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/headsail-bsp/src/lib.rs b/examples/headsail-bsp/src/lib.rs index 8c36a0cc..741ed8bb 100644 --- a/examples/headsail-bsp/src/lib.rs +++ b/examples/headsail-bsp/src/lib.rs @@ -6,6 +6,7 @@ pub mod uart; #[cfg(feature = "hpc")] pub use hpc::*; +pub use riscv; #[cfg(feature = "rt")] pub use riscv_rt as rt; pub use ufmt;