diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index d0eb9ab1..67fbb920 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `mie` register
 - Use CSR helper macros to define `mimpid` register
 - Use CSR helper macros to define `misa` register
+- Use CSR helper macros to define `mip` register
 
 ## [v0.12.1] - 2024-10-20
 
diff --git a/riscv/src/register/mip.rs b/riscv/src/register/mip.rs
index dcf126e7..bfcb8936 100644
--- a/riscv/src/register/mip.rs
+++ b/riscv/src/register/mip.rs
@@ -54,3 +54,25 @@ set_clear_csr!(
 set_clear_csr!(
     /// Supervisor External Interrupt Pending
     , set_sext, clear_sext, 1 << 9);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mip() {
+        let mut m = Mip::from_bits(0);
+
+        test_csr_field!(m, ssoft);
+        test_csr_field!(m, stimer);
+        test_csr_field!(m, sext);
+
+        assert!(!m.msoft());
+        assert!(!m.mtimer());
+        assert!(!m.mext());
+
+        assert!(Mip::from_bits(1 << 3).msoft());
+        assert!(Mip::from_bits(1 << 7).mtimer());
+        assert!(Mip::from_bits(1 << 11).mext());
+    }
+}