From 89709cb0c10783e67f0924b761e261feb7c0a68d Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 20 Oct 2023 16:49:26 -0500 Subject: [PATCH 01/19] Remove macros checking for CS_API_VERSION 3 --- librz/analysis/arch/arm/arm_accessors32.h | 5 ----- librz/analysis/arch/arm/arm_accessors64.h | 4 ---- librz/analysis/arch/arm/arm_esil64.c | 2 -- librz/analysis/arch/arm/arm_il32.c | 26 ----------------------- librz/analysis/arch/arm/arm_il64.c | 6 ------ librz/analysis/arch/ppc/ppc_il.c | 10 --------- librz/analysis/arch/ppc/ppc_il_ops.c | 12 ----------- librz/analysis/arch/x86/common.c | 5 ----- librz/analysis/p/analysis_arm_cs.c | 6 ------ librz/analysis/p/analysis_mips_cs.c | 2 -- librz/analysis/p/analysis_x86_cs.c | 4 ---- librz/asm/p/asm_mips_cs.c | 2 -- 12 files changed, 84 deletions(-) diff --git a/librz/analysis/arch/arm/arm_accessors32.h b/librz/analysis/arch/arm/arm_accessors32.h index 7d3d5b06858..c18e2edba8f 100644 --- a/librz/analysis/arch/arm/arm_accessors32.h +++ b/librz/analysis/arch/arm/arm_accessors32.h @@ -25,13 +25,8 @@ #define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM) #define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP) -#if CS_API_MAJOR > 3 #define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift #define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL -#else -#define LSHIFT(x) 0 -#define LSHIFT2(x) 0 -#endif #define OPCOUNT() insn->detail->arm.op_count #define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0) #define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type diff --git a/librz/analysis/arch/arm/arm_accessors64.h b/librz/analysis/arch/arm/arm_accessors64.h index d1c1caee956..67304d31d3a 100644 --- a/librz/analysis/arch/arm/arm_accessors64.h +++ b/librz/analysis/arch/arm/arm_accessors64.h @@ -21,11 +21,7 @@ #define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG) #define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM) -#if CS_API_MAJOR > 3 #define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value -#else -#define LSHIFT2_64(x) 0 -#endif #define OPCOUNT64() insn->detail->arm64.op_count #define ISWRITEBACK64() (insn->detail->arm64.writeback == true) diff --git a/librz/analysis/arch/arm/arm_esil64.c b/librz/analysis/arch/arm/arm_esil64.c index 30e04b51635..eea43f5bdba 100644 --- a/librz/analysis/arch/arm/arm_esil64.c +++ b/librz/analysis/arch/arm/arm_esil64.c @@ -1127,9 +1127,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; case ARM64_INS_NEG: -#if CS_API_MAJOR > 3 case ARM64_INS_NEGS: -#endif if (LSHIFT2_64(1)) { SHIFTED_REG64_APPEND(&op->esil, 1); } else { diff --git a/librz/analysis/arch/arm/arm_il32.c b/librz/analysis/arch/arm/arm_il32.c index 4f5cbc68829..e3fca1a1b2e 100644 --- a/librz/analysis/arch/arm/arm_il32.c +++ b/librz/analysis/arch/arm/arm_il32.c @@ -264,11 +264,7 @@ static inline RzFloatFormat cvtdt2fmt(arm_vectordata_type type, bool choose_src) #define VVEC_DT(insn) insn->detail->arm.vector_data #define FROM_FMT(dt) cvtdt2fmt(dt, true) #define TO_FMT(dt) cvtdt2fmt(dt, false) -#if CS_API_MAJOR > 3 -// clang-format off #define NEON_LANE(n) insn->detail->arm.operands[n].neon_lane -// clang-format on -#endif /** * IL to write the given capstone reg @@ -1371,8 +1367,6 @@ static void label_svc(RzILVM *vm, RzILOpEffect *op) { // stub, nothing to do here } -#if CS_API_MAJOR > 3 - /** * Capstone: ARM_INS_HVC * ARM: hvc @@ -1381,8 +1375,6 @@ static RzILOpEffect *hvc(cs_insn *insn, bool is_thumb) { return GOTO("hvc"); } -#endif - static void label_hvc(RzILVM *vm, RzILOpEffect *op) { // stub, nothing to do here } @@ -2591,7 +2583,6 @@ static RzILOpEffect *write_reg_lane(arm_reg reg, ut32 lane, ut32 vec_size, RzILO * VFP and NEON */ -#if CS_API_MAJOR > 3 /** * Capstone: ARM_INS_VMOV * ARM: vmov @@ -2708,7 +2699,6 @@ static RzILOpEffect *vmov(cs_insn *insn, bool is_thumb) { return write_reg(REGID(0), val); } -#endif /** * Capstone: ARM_INS_VMRS @@ -3088,7 +3078,6 @@ static RzILOpEffect *vldn_multiple_elem(cs_insn *insn, bool is_thumb) { return SEQ2(eff, wback_eff); } -#if CS_API_MAJOR > 3 static RzILOpEffect *vldn_single_lane(cs_insn *insn, bool is_thumb) { ut32 mem_idx; bool use_rm_as_wback_offset = false; @@ -3170,7 +3159,6 @@ static RzILOpEffect *vldn_single_lane(cs_insn *insn, bool is_thumb) { return SEQ2(eff, wback_eff); } -#endif static RzILOpEffect *vldn_all_lane(cs_insn *insn, bool is_thumb) { ut32 mem_idx; @@ -3261,12 +3249,10 @@ static RzILOpEffect *vldn(cs_insn *insn, bool is_thumb) { return NULL; } -#if CS_API_MAJOR > 3 // to single lane if (NEON_LANE(0) != -1) { return vldn_single_lane(insn, is_thumb); } -#endif // TODO: capstone cannot distinguish details of the following instructions // vld3.8 {d0, d1, d2}, [r0] (f420040f) @@ -3365,7 +3351,6 @@ static RzILOpEffect *vstn_multiple_elem(cs_insn *insn, bool is_thumb) { return SEQ2(eff, wback_eff); } -#if CS_API_MAJOR > 3 static RzILOpEffect *vstn_from_single_lane(cs_insn *insn, bool is_thumb) { ut32 mem_idx; bool use_rm_as_wback_offset = false; @@ -3446,18 +3431,15 @@ static RzILOpEffect *vstn_from_single_lane(cs_insn *insn, bool is_thumb) { return SEQ2(eff, wback_eff); } -#endif static RzILOpEffect *vstn(cs_insn *insn, bool is_thumb) { if (OPCOUNT() < 2 || !ISREG(0)) { return NULL; } -#if CS_API_MAJOR > 3 if (NEON_LANE(0) != -1) { return vstn_from_single_lane(insn, is_thumb); } -#endif return vstn_multiple_elem(insn, is_thumb); } @@ -3622,7 +3604,6 @@ static RzILOpEffect *vcvt(cs_insn *insn, bool is_thumb) { return NULL; } -#if CS_API_MAJOR > 3 static RzILOpEffect *vdup(cs_insn *insn, bool is_thumb) { if (OPCOUNT() < 2) { return NULL; @@ -3643,7 +3624,6 @@ static RzILOpEffect *vdup(cs_insn *insn, bool is_thumb) { return eff; } -#endif static RzILOpEffect *vext(cs_insn *insn, bool is_thumb) { if (OPCOUNT() < 2) { @@ -4144,10 +4124,8 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb) return clz(insn, is_thumb); case ARM_INS_SVC: return svc(insn, is_thumb); -#if CS_API_MAJOR > 3 case ARM_INS_HVC: return hvc(insn, is_thumb); -#endif case ARM_INS_BFC: return bfc(insn, is_thumb); case ARM_INS_BFI: @@ -4302,11 +4280,9 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb) case ARM_INS_VMOVN: case ARM_INS_VMOVX: #endif -#if CS_API_MAJOR > 3 case ARM_INS_VMOV: case ARM_INS_VMVN: return vmov(insn, is_thumb); -#endif case ARM_INS_VMSR: return vmsr(insn, is_thumb); case ARM_INS_VMRS: @@ -4353,10 +4329,8 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb) case ARM_INS_VCVTT: #endif return vcvt(insn, is_thumb); -#if CS_API_MAJOR > 3 case ARM_INS_VDUP: return vdup(insn, is_thumb); -#endif case ARM_INS_VEXT: return vext(insn, is_thumb); case ARM_INS_VZIP: diff --git a/librz/analysis/arch/arm/arm_il64.c b/librz/analysis/arch/arm/arm_il64.c index 70a29ae230b..645bc6d1104 100644 --- a/librz/analysis/arch/arm/arm_il64.c +++ b/librz/analysis/arch/arm/arm_il64.c @@ -1838,15 +1838,11 @@ static RzILOpEffect *mvn(cs_insn *insn) { RzILOpBitVector *res; switch (insn->id) { case ARM64_INS_NEG: -#if CS_API_MAJOR > 3 case ARM64_INS_NEGS: -#endif res = NEG(val); break; case ARM64_INS_NGC: -#if CS_API_MAJOR > 3 case ARM64_INS_NGCS: -#endif res = NEG(ADD(val, ITE(VARG("cf"), UN(bits, 0), UN(bits, 1)))); break; default: // ARM64_INS_MVN @@ -2652,10 +2648,8 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case ARM64_INS_MVN: case ARM64_INS_NEG: case ARM64_INS_NGC: -#if CS_API_MAJOR > 3 case ARM64_INS_NEGS: case ARM64_INS_NGCS: -#endif return mvn(insn); case ARM64_INS_RBIT: return rbit(insn); diff --git a/librz/analysis/arch/ppc/ppc_il.c b/librz/analysis/arch/ppc/ppc_il.c index 5bc9662e66e..dd8f1b45cb4 100644 --- a/librz/analysis/arch/ppc/ppc_il.c +++ b/librz/analysis/arch/ppc/ppc_il.c @@ -60,7 +60,6 @@ RZ_IPI bool ppc_is_x_form(ut32 insn_id) { case PPC_INS_STDX: case PPC_INS_STDCX: case PPC_INS_STWCX: -#if CS_API_MAJOR > 3 case PPC_INS_LBZCIX: case PPC_INS_LDCIX: case PPC_INS_LHZCIX: @@ -69,7 +68,6 @@ RZ_IPI bool ppc_is_x_form(ut32 insn_id) { case PPC_INS_STHCIX: case PPC_INS_STWCIX: case PPC_INS_STDCIX: -#endif return true; } } @@ -101,10 +99,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) { case PPC_INS_STBU: case PPC_INS_STBUX: case PPC_INS_STBX: -#if CS_API_MAJOR > 3 case PPC_INS_STBCIX: case PPC_INS_LBZCIX: -#endif return PPC_BYTE; case PPC_INS_LHA: case PPC_INS_LHAU: @@ -120,10 +116,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) { case PPC_INS_STHU: case PPC_INS_STHUX: case PPC_INS_STHX: -#if CS_API_MAJOR > 3 case PPC_INS_LHZCIX: case PPC_INS_STHCIX: -#endif return PPC_HWORD; case PPC_INS_LWA: case PPC_INS_LWARX: @@ -142,10 +136,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) { case PPC_INS_STWUX: case PPC_INS_STWX: case PPC_INS_STMW: -#if CS_API_MAJOR > 3 case PPC_INS_LWZCIX: case PPC_INS_STWCIX: -#endif return PPC_WORD; case PPC_INS_LD: case PPC_INS_LDARX: @@ -159,10 +151,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) { case PPC_INS_STDU: case PPC_INS_STDUX: case PPC_INS_STDX: -#if CS_API_MAJOR > 3 case PPC_INS_LDCIX: case PPC_INS_STDCIX: -#endif return PPC_DWORD; } } diff --git a/librz/analysis/arch/ppc/ppc_il_ops.c b/librz/analysis/arch/ppc/ppc_il_ops.c index f39aab2172d..7be7b9766dd 100644 --- a/librz/analysis/arch/ppc/ppc_il_ops.c +++ b/librz/analysis/arch/ppc/ppc_il_ops.c @@ -84,12 +84,10 @@ static RzILOpEffect *load_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, cons case PPC_INS_LWA: case PPC_INS_LWAX: case PPC_INS_LWAUX: -#if CS_API_MAJOR > 3 case PPC_INS_LBZCIX: case PPC_INS_LHZCIX: case PPC_INS_LWZCIX: case PPC_INS_LDCIX: -#endif #if CS_NEXT_VERSION >= 6 base = VARG(rA); #else @@ -275,12 +273,10 @@ static RzILOpEffect *store_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, con case PPC_INS_STHUX: case PPC_INS_STWUX: case PPC_INS_STDUX: -#if CS_API_MAJOR > 3 case PPC_INS_STBCIX: case PPC_INS_STHCIX: case PPC_INS_STWCIX: case PPC_INS_STDCIX: -#endif #if CS_NEXT_VERSION >= 6 base = VARG(rA); #else @@ -667,7 +663,6 @@ static RzILOpEffect *bitwise_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, c res = LOGNOT( (id == PPC_INS_NAND) ? LOGAND(op0, op1) : LOGOR(op0, op1)); break; -#if CS_API_MAJOR > 3 // Compare bytes case PPC_INS_CMPB: { // do n = 0 to (64BIT_CPU ? 7 : 3) @@ -700,7 +695,6 @@ static RzILOpEffect *bitwise_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, c return SEQ5(SETL("res", UA(0)), init_n, init_bitmask, loop, SETG(rA, VARL("res"))); } -#endif case PPC_INS_EQV: op0 = VARG(rS); op1 = VARG(rB); @@ -1504,12 +1498,10 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_LWZU: case PPC_INS_LWZUX: case PPC_INS_LWZX: -#if CS_API_MAJOR > 3 case PPC_INS_LBZCIX: case PPC_INS_LHZCIX: case PPC_INS_LWZCIX: case PPC_INS_LDCIX: -#endif lop = load_op(handle, insn, mode); break; case PPC_INS_STB: @@ -1553,12 +1545,10 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_STXVD2X: case PPC_INS_STXVW4X: case PPC_INS_DCBZ: -#if CS_API_MAJOR > 3 case PPC_INS_STHCIX: case PPC_INS_STWCIX: case PPC_INS_STBCIX: case PPC_INS_STDCIX: -#endif lop = store_op(handle, insn, mode); break; #if CS_NEXT_VERSION < 6 @@ -1593,9 +1583,7 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_CNTLZW: case PPC_INS_POPCNTD: case PPC_INS_POPCNTW: -#if CS_API_MAJOR > 3 case PPC_INS_CMPB: -#endif #if CS_API_MAJOR == 5 case PPC_INS_CMPRB: case PPC_INS_CMPEQB: diff --git a/librz/analysis/arch/x86/common.c b/librz/analysis/arch/x86/common.c index b4e605e6839..d6c563d9617 100644 --- a/librz/analysis/arch/x86/common.c +++ b/librz/analysis/arch/x86/common.c @@ -742,11 +742,6 @@ RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int im return SN(op.size * BITS_PER_BYTE, op.imm); case X86_OP_MEM: return LOADW(BITS_PER_BYTE * op.size, x86_il_get_memaddr_bits(op.mem, analysis_bits, pc)); -#if CS_API_MAJOR <= 3 - case X86_OP_FP: - RZ_LOG_WARN("RzIL: x86: Floating point instructions not implemented yet\n"); - return NULL; -#endif default: return NULL; } diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index d3f41565ef4..c11566df2f6 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -807,9 +807,7 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->type = RZ_ANALYSIS_OP_TYPE_SAR; break; case ARM64_INS_NEG: -#if CS_API_MAJOR > 3 case ARM64_INS_NEGS: -#endif op->type = RZ_ANALYSIS_OP_TYPE_NOT; break; case ARM64_INS_FCMP: @@ -1606,9 +1604,7 @@ static void set_src_dst(RzAnalysisValue *val, RzReg *reg, csh *handle, cs_insn * break; case ARM_OP_MEM: val->type = RZ_ANALYSIS_VAL_MEM; -#if CS_API_MAJOR > 3 val->mul = armop.mem.scale << armop.mem.lshift; -#endif #if CS_NEXT_VERSION == 6 val->delta = MEMDISP(x); #else @@ -1658,7 +1654,6 @@ static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh handle, cs_in case RZ_ANALYSIS_OP_TYPE_ROL: case RZ_ANALYSIS_OP_TYPE_CAST: for (i = 1; i < count; i++) { -#if CS_API_MAJOR > 3 if (bits == 64) { cs_arm64_op arm64op = INSOP64(i); if (arm64op.access == CS_AC_WRITE) { @@ -1671,7 +1666,6 @@ static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh handle, cs_in continue; } } -#endif break; } for (j = 0; j < 3; j++, i++) { diff --git a/librz/analysis/p/analysis_mips_cs.c b/librz/analysis/p/analysis_mips_cs.c index 1b994580a34..ca14cef7c41 100644 --- a/librz/analysis/p/analysis_mips_cs.c +++ b/librz/analysis/p/analysis_mips_cs.c @@ -733,9 +733,7 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u } else if (!strcmp(analysis->cpu, "v3")) { mode |= CS_MODE_MIPS3; } else if (!strcmp(analysis->cpu, "v2")) { -#if CS_API_MAJOR > 3 mode |= CS_MODE_MIPS2; -#endif } } switch (analysis->bits) { diff --git a/librz/analysis/p/analysis_x86_cs.c b/librz/analysis/p/analysis_x86_cs.c index c9caa2d0297..ce6597fe7a2 100644 --- a/librz/analysis/p/analysis_x86_cs.c +++ b/librz/analysis/p/analysis_x86_cs.c @@ -250,10 +250,6 @@ static char *getarg(struct Getarg *gop, int n, int set, char *setop, int sel, ut *bitsize = op.size * 8; } switch (op.type) { -#if CS_API_MAJOR == 3 - case X86_OP_FP: - return "invalid"; -#endif case X86_OP_INVALID: return "invalid"; case X86_OP_REG: diff --git a/librz/asm/p/asm_mips_cs.c b/librz/asm/p/asm_mips_cs.c index 0cd1edd2952..7753e752afc 100644 --- a/librz/asm/p/asm_mips_cs.c +++ b/librz/asm/p/asm_mips_cs.c @@ -25,9 +25,7 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { } else if (!strcmp(a->cpu, "v3")) { mode |= CS_MODE_MIPS3; } else if (!strcmp(a->cpu, "v2")) { -#if CS_API_MAJOR > 3 mode |= CS_MODE_MIPS2; -#endif } } mode |= (a->bits == 64) ? CS_MODE_MIPS64 : CS_MODE_MIPS32; From 65b09b4c8e879a3063b72d7a5dcb62b6d87c34c9 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 20 Oct 2023 16:51:33 -0500 Subject: [PATCH 02/19] Remove CS 3 from meson_options and subprojects. --- meson_options.txt | 2 +- .../capstone-3.0.5/include/capstone/arm.h | 4 - .../capstone-3.0.5/include/capstone/arm64.h | 4 - .../include/capstone/capstone.h | 4 - .../capstone-3.0.5/include/capstone/mips.h | 4 - .../include/capstone/platform.h | 4 - .../capstone-3.0.5/include/capstone/ppc.h | 4 - .../capstone-3.0.5/include/capstone/sparc.h | 4 - .../capstone-3.0.5/include/capstone/systemz.h | 4 - .../capstone-3.0.5/include/capstone/x86.h | 4 - .../capstone-3.0.5/include/capstone/xcore.h | 4 - .../packagefiles/capstone-3.0.5/meson.build | 81 ------------------- 12 files changed, 1 insertion(+), 122 deletions(-) delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/arm.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/arm64.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/capstone.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/mips.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/platform.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/ppc.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/sparc.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/systemz.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/x86.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/include/capstone/xcore.h delete mode 100644 subprojects/packagefiles/capstone-3.0.5/meson.build diff --git a/meson_options.txt b/meson_options.txt index 3f463091bc0..e51701f7686 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -20,7 +20,7 @@ option('rizin_bindings', type: 'string', value: '', description: 'Path where riz option('checks_level', type: 'integer', value: 9999, description: 'Value between 0 and 3 to enable different level of assert (see RZ_CHECKS_LEVEL). By default its value depends on buildtype (2 on debug, 1 on release).') option('use_sys_capstone', type: 'feature', value: 'disabled') -option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'v5', 'next'], value: 'next', description: 'Specify which version of capstone to use') +option('use_capstone_version', type: 'combo', choices: ['v4', 'v5', 'next'], value: 'next', description: 'Specify which version of capstone to use') option('use_sys_magic', type: 'feature', value: 'disabled') option('use_sys_libzip', type: 'feature', value: 'disabled') option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip') diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/arm.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/arm.h deleted file mode 100644 index 67b4901a6df..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/arm.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../arm.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/arm64.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/arm64.h deleted file mode 100644 index 44f29981b45..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/arm64.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../arm64.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/capstone.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/capstone.h deleted file mode 100644 index 873639e3ddb..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/capstone.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../capstone.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/mips.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/mips.h deleted file mode 100644 index 412f0782a11..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/mips.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../mips.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/platform.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/platform.h deleted file mode 100644 index a24b29b2f31..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/platform.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../platform.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/ppc.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/ppc.h deleted file mode 100644 index 70222922f2b..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/ppc.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../ppc.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/sparc.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/sparc.h deleted file mode 100644 index f3010b1ead3..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/sparc.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../sparc.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/systemz.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/systemz.h deleted file mode 100644 index 8584378a32a..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/systemz.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../systemz.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/x86.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/x86.h deleted file mode 100644 index dc4bfe07787..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/x86.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../x86.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/include/capstone/xcore.h b/subprojects/packagefiles/capstone-3.0.5/include/capstone/xcore.h deleted file mode 100644 index 7320f2f6b34..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/include/capstone/xcore.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2022 hamari -// SPDX-License-Identifier: LGPL-3.0-only - -#include "../xcore.h" diff --git a/subprojects/packagefiles/capstone-3.0.5/meson.build b/subprojects/packagefiles/capstone-3.0.5/meson.build deleted file mode 100644 index 70c35888265..00000000000 --- a/subprojects/packagefiles/capstone-3.0.5/meson.build +++ /dev/null @@ -1,81 +0,0 @@ -project('capstone', 'c', version: '3.0.5', meson_version: '>=0.55.0') - -cs_files = [ - 'arch/AArch64/AArch64BaseInfo.c', - 'arch/AArch64/AArch64Disassembler.c', - 'arch/AArch64/AArch64InstPrinter.c', - 'arch/AArch64/AArch64Mapping.c', - 'arch/AArch64/AArch64Module.c', - 'arch/ARM/ARMDisassembler.c', - 'arch/ARM/ARMInstPrinter.c', - 'arch/ARM/ARMMapping.c', - 'arch/ARM/ARMModule.c', - 'arch/Mips/MipsDisassembler.c', - 'arch/Mips/MipsInstPrinter.c', - 'arch/Mips/MipsMapping.c', - 'arch/Mips/MipsModule.c', - 'arch/PowerPC/PPCDisassembler.c', - 'arch/PowerPC/PPCInstPrinter.c', - 'arch/PowerPC/PPCMapping.c', - 'arch/PowerPC/PPCModule.c', - 'arch/Sparc/SparcDisassembler.c', - 'arch/Sparc/SparcInstPrinter.c', - 'arch/Sparc/SparcMapping.c', - 'arch/Sparc/SparcModule.c', - 'arch/SystemZ/SystemZDisassembler.c', - 'arch/SystemZ/SystemZInstPrinter.c', - 'arch/SystemZ/SystemZMapping.c', - 'arch/SystemZ/SystemZMCTargetDesc.c', - 'arch/SystemZ/SystemZModule.c', - 'arch/X86/X86ATTInstPrinter.c', - 'arch/X86/X86Disassembler.c', - 'arch/X86/X86DisassemblerDecoder.c', - 'arch/X86/X86IntelInstPrinter.c', - 'arch/X86/X86Mapping.c', - 'arch/X86/X86Module.c', - 'arch/XCore/XCoreDisassembler.c', - 'arch/XCore/XCoreInstPrinter.c', - 'arch/XCore/XCoreMapping.c', - 'arch/XCore/XCoreModule.c', - 'cs.c', - 'MCInst.c', - 'MCInstrDesc.c', - 'MCRegisterInfo.c', - 'SStream.c', - 'utils.c', -] - -capstone_includes = [include_directories('include')] - -libcapstone_c_args = [ - '-DCAPSTONE_X86_ATT_DISABLE_NO', - '-DCAPSTONE_X86_REDUCE_NO', - '-DCAPSTONE_USE_SYS_DYN_MEM', - '-DCAPSTONE_DIET_NO', - '-DCAPSTONE_HAS_ARM', - '-DCAPSTONE_HAS_ARM64', - '-DCAPSTONE_HAS_M68K', - '-DCAPSTONE_HAS_M680X', - '-DCAPSTONE_HAS_MIPS', - '-DCAPSTONE_HAS_POWERPC', - '-DCAPSTONE_HAS_SPARC', - '-DCAPSTONE_HAS_SYSZ', - '-DCAPSTONE_HAS_X86', - '-DCAPSTONE_HAS_XCORE', - '-DCAPSTONE_HAS_TMS320C64X', -] -warn_trunc_flag = '-Wno-error=stringop-truncation' -if meson.get_compiler('c').has_argument(warn_trunc_flag) - libcapstone_c_args += warn_trunc_flag -endif - -libcapstone = library('capstone', cs_files, - c_args: libcapstone_c_args, - include_directories: capstone_includes, - implicit_include_directories: false -) - -capstone_dep = declare_dependency( - link_with: libcapstone, - include_directories: capstone_includes -) From b603ab3e792e3fd0553ed9de4fdc558db4043221 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 20 Oct 2023 16:59:22 -0500 Subject: [PATCH 03/19] Remove Capstone v3 from CI --- .github/workflows/ci.yml | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index c9723ec04b2..4410e47a0f1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -62,7 +62,6 @@ jobs: linux-gcc-tests-asan, linux-clang-tests-asan, linux-gcc-tests-codecov, - capstone-v3, capstone-v4, ] include: @@ -129,16 +128,6 @@ jobs: timeout: 60 cflags: "-Wno-cpp" allow_failure: false - - name: capstone-v3 - os: ubuntu-22.04 - build_system: meson - compiler: gcc - meson_options: -Dbuildtype=release -Duse_capstone_version=v3 --werror - run_tests: false - enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }} - timeout: 45 - cflags: "-Wno-cpp" - allow_failure: false - name: capstone-sys os: ubuntu-22.04 build_system: meson From 3572870b39d4f021644ca77dc092cf750a6b725d Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 20 Oct 2023 17:02:55 -0500 Subject: [PATCH 04/19] Run clang-format --- librz/analysis/arch/arm/arm_accessors32.h | 4 ++-- librz/analysis/arch/arm/arm_accessors64.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/librz/analysis/arch/arm/arm_accessors32.h b/librz/analysis/arch/arm/arm_accessors32.h index c18e2edba8f..a8669819619 100644 --- a/librz/analysis/arch/arm/arm_accessors32.h +++ b/librz/analysis/arch/arm/arm_accessors32.h @@ -25,8 +25,8 @@ #define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM) #define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP) -#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift -#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL +#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift +#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL #define OPCOUNT() insn->detail->arm.op_count #define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0) #define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type diff --git a/librz/analysis/arch/arm/arm_accessors64.h b/librz/analysis/arch/arm/arm_accessors64.h index 67304d31d3a..213ebc70dd2 100644 --- a/librz/analysis/arch/arm/arm_accessors64.h +++ b/librz/analysis/arch/arm/arm_accessors64.h @@ -22,7 +22,7 @@ #define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM) #define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value -#define OPCOUNT64() insn->detail->arm64.op_count +#define OPCOUNT64() insn->detail->arm64.op_count #define ISWRITEBACK64() (insn->detail->arm64.writeback == true) #define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64()))) From 074f5fe39c8212c65955b044133666ce713c8df8 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 20 Oct 2023 17:09:57 -0500 Subject: [PATCH 05/19] Remove CS_API_VERSION >= 4 checks since always true from now on. --- librz/analysis/arch/x86/common.c | 2 -- librz/analysis/p/analysis_arm_cs.c | 4 ---- librz/analysis/p/analysis_m680x_cs.c | 24 ------------------------ librz/analysis/p/analysis_m68k_cs.c | 7 ------- librz/analysis/p/analysis_ppc_cs.c | 8 -------- librz/analysis/p/analysis_x86_cs.c | 26 -------------------------- librz/asm/p/asm_m680x_cs.c | 18 ------------------ librz/asm/p/asm_x86_cs.c | 4 ---- 8 files changed, 93 deletions(-) diff --git a/librz/analysis/arch/x86/common.c b/librz/analysis/arch/x86/common.c index d6c563d9617..16faae233af 100644 --- a/librz/analysis/arch/x86/common.c +++ b/librz/analysis/arch/x86/common.c @@ -81,7 +81,6 @@ const char *x86_registers[X86_REG_ENDING] = { [X86_REG_DR5] = "dr5", [X86_REG_DR6] = "dr6", [X86_REG_DR7] = "dr7", -#if CS_API_MAJOR >= 4 [X86_REG_DR8] = "dr8", [X86_REG_DR9] = "dr9", [X86_REG_DR10] = "dr10", @@ -90,7 +89,6 @@ const char *x86_registers[X86_REG_ENDING] = { [X86_REG_DR13] = "dr13", [X86_REG_DR14] = "dr14", [X86_REG_DR15] = "dr15", -#endif [X86_REG_FP0] = "fp0", [X86_REG_FP1] = "fp1", [X86_REG_FP2] = "fp2", diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index c11566df2f6..4ddf6ccfeae 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -571,10 +571,8 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; } else if (cs_insn_group(handle, insn, ARM64_GRP_CRC)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; -#if CS_API_MAJOR >= 4 } else if (cs_insn_group(handle, insn, ARM64_GRP_PRIVILEGE)) { op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; -#endif } else if (cs_insn_group(handle, insn, ARM64_GRP_NEON)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; } else if (cs_insn_group(handle, insn, ARM64_GRP_FPARMV8)) { @@ -1019,12 +1017,10 @@ static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, b op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasCRC)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; -#if CS_API_MAJOR >= 4 } else if (cs_insn_group(handle, insn, ARM_GRP_PRIVILEGE)) { op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasVirtualization)) { op->family = RZ_ANALYSIS_OP_FAMILY_VIRT; -#endif } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasNEON)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasFPARMv8)) { diff --git a/librz/analysis/p/analysis_m680x_cs.c b/librz/analysis/p/analysis_m680x_cs.c index 97e10b8b15b..c6805f87f5f 100644 --- a/librz/analysis/p/analysis_m680x_cs.c +++ b/librz/analysis/p/analysis_m680x_cs.c @@ -5,21 +5,6 @@ #include #include -#if CS_API_MAJOR >= 4 && CS_API_MINOR >= 0 -#define CAPSTONE_HAS_M680X 1 -#else -#define CAPSTONE_HAS_M680X 0 -#endif - -#if !CAPSTONE_HAS_M680X -#ifdef _MSC_VER -#pragma message("Cannot find support for m680x in capstone") -#else -#warning Cannot find capstone-m680x support -#endif -#endif - -#if CAPSTONE_HAS_M680X #include static int m680xmode(const char *str) { @@ -538,15 +523,6 @@ RzAnalysisPlugin rz_analysis_plugin_m680x_cs = { .bits = 16 | 32, .op = &analyze_op, }; -#else -RzAnalysisPlugin rz_analysis_plugin_m680x_cs = { - .name = "m680x (unsupported)", - .desc = "Capstone M680X analyzer (unsupported)", - .license = "BSD", - .arch = "m680x", - .bits = 32, -}; -#endif #ifndef RZ_PLUGIN_INCORE RZ_API RzLibStruct rizin_plugin = { diff --git a/librz/analysis/p/analysis_m68k_cs.c b/librz/analysis/p/analysis_m68k_cs.c index 67fcd4dda91..e227087d955 100644 --- a/librz/analysis/p/analysis_m68k_cs.c +++ b/librz/analysis/p/analysis_m68k_cs.c @@ -32,19 +32,12 @@ static inline ut64 make_64bits_address(ut64 address) { } static inline void handle_branch_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, ut32 type, int index) { -#if CS_API_MAJOR >= 4 if (m68k->operands[index].type == M68K_OP_BR_DISP) { op->type = type; // TODO: disp_size is ignored op->jump = make_64bits_address(addr + m68k->operands[index].br_disp.disp + 2); op->fail = make_64bits_address(addr + op->size); } -#else - op->type = type; - // TODO: disp_size is ignored - op->jump = make_64bits_address(addr + m68k->operands[index].br_disp.disp + 2); - op->fail = make_64bits_address(addr + op->size); -#endif } static inline void handle_jump_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, ut32 type) { diff --git a/librz/analysis/p/analysis_ppc_cs.c b/librz/analysis/p/analysis_ppc_cs.c index 83dd3353d09..cf118f94c8a 100644 --- a/librz/analysis/p/analysis_ppc_cs.c +++ b/librz/analysis/p/analysis_ppc_cs.c @@ -981,9 +981,7 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf op->size = insn->size; op->id = insn->id; switch (insn->id) { -#if CS_API_MAJOR >= 4 case PPC_INS_CMPB: -#endif case PPC_INS_CMPD: case PPC_INS_CMPDI: case PPC_INS_CMPLD: @@ -1137,9 +1135,7 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf esilprintf(op, "%s,%s,=[8],%s=", ARG(0), op1, op1); break; case PPC_INS_LBZ: -#if CS_API_MAJOR >= 4 case PPC_INS_LBZCIX: -#endif case PPC_INS_LBZU: case PPC_INS_LBZUX: op->type = RZ_ANALYSIS_OP_TYPE_LOAD; @@ -1155,9 +1151,7 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf break; case PPC_INS_LD: case PPC_INS_LDARX: -#if CS_API_MAJOR >= 4 case PPC_INS_LDCIX: -#endif case PPC_INS_LDU: case PPC_INS_LDUX: op->type = RZ_ANALYSIS_OP_TYPE_LOAD; @@ -1208,9 +1202,7 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf case PPC_INS_LWAUX: case PPC_INS_LWAX: case PPC_INS_LWZ: -#if CS_API_MAJOR >= 4 case PPC_INS_LWZCIX: -#endif case PPC_INS_LWZX: op->type = RZ_ANALYSIS_OP_TYPE_LOAD; esilprintf(op, "%s,%s,=", ARG2(1, "[4]"), ARG(0)); diff --git a/librz/analysis/p/analysis_x86_cs.c b/librz/analysis/p/analysis_x86_cs.c index ce6597fe7a2..8d050cc092c 100644 --- a/librz/analysis/p/analysis_x86_cs.c +++ b/librz/analysis/p/analysis_x86_cs.c @@ -88,13 +88,11 @@ static void hidden_op(cs_insn *insn, cs_x86 *x, int mode) { op->type = X86_OP_REG; op->reg = X86_REG_EFLAGS; op->size = regsz; -#if CS_API_MAJOR >= 4 if (id == X86_INS_PUSHF || id == X86_INS_PUSHFD || id == X86_INS_PUSHFQ) { op->access = 1; } else { op->access = 2; } -#endif break; case X86_INS_PUSHAW: case X86_INS_PUSHAL: @@ -122,9 +120,7 @@ static void opex(RzStrBuf *buf, X86CSContext *ctx, int mode) { cs_x86_op *op = x->operands + i; pj_o(pj); pj_ki(pj, "size", op->size); -#if CS_API_MAJOR >= 4 pj_ki(pj, "rw", op->access); // read, write, read|write -#endif switch (op->type) { case X86_OP_REG: pj_ks(pj, "type", "reg"); @@ -431,9 +427,7 @@ static void anop_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf case X86_INS_FPREM: case X86_INS_FPREM1: case X86_INS_FPTAN: -#if CS_API_MAJOR >= 4 case X86_INS_FFREEP: -#endif case X86_INS_FRNDINT: case X86_INS_FRSTOR: case X86_INS_FNSAVE: @@ -514,9 +508,7 @@ static void anop_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf case X86_INS_CLAC: case X86_INS_CLGI: case X86_INS_CLTS: -#if CS_API_MAJOR >= 4 case X86_INS_CLWB: -#endif case X86_INS_STAC: case X86_INS_STGI: break; @@ -1905,7 +1897,6 @@ static void set_access_info(RzReg *reg, RzAnalysisOp *op, csh *handle, cs_insn * val->reg = cs_reg2reg(reg, handle, ip); rz_list_append(ret, val); -#if CS_API_MAJOR >= 4 // Register access info cs_regs regs_read, regs_write; ut8 read_count, write_count; @@ -1929,7 +1920,6 @@ static void set_access_info(RzReg *reg, RzAnalysisOp *op, csh *handle, cs_insn * } } } -#endif switch (insn->id) { case X86_INS_PUSH: @@ -2007,7 +1997,6 @@ static void set_access_info(RzReg *reg, RzAnalysisOp *op, csh *handle, cs_insn * if (INSOP(i).type == X86_OP_MEM) { val = rz_analysis_value_new(); val->type = RZ_ANALYSIS_VAL_MEM; -#if CS_API_MAJOR >= 4 switch (INSOP(i).access) { case CS_AC_READ: val->access = RZ_ANALYSIS_ACC_R; @@ -2019,9 +2008,6 @@ static void set_access_info(RzReg *reg, RzAnalysisOp *op, csh *handle, cs_insn * val->access = RZ_ANALYSIS_ACC_UNKNOWN; break; } -#else - val->access = RZ_ANALYSIS_ACC_UNKNOWN; -#endif val->mul = INSOP(i).mem.scale; val->delta = INSOP(i).mem.disp; if (INSOP(0).mem.base == X86_REG_RIP || @@ -2255,9 +2241,7 @@ static void anop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int case X86_INS_FPREM: case X86_INS_FPREM1: case X86_INS_FPTAN: -#if CS_API_MAJOR >= 4 case X86_INS_FFREEP: -#endif case X86_INS_FRNDINT: case X86_INS_FRSTOR: case X86_INS_FNSAVE: @@ -2352,9 +2336,7 @@ static void anop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int case X86_INS_CLAC: case X86_INS_CLGI: case X86_INS_CLTS: -#if CS_API_MAJOR >= 4 case X86_INS_CLWB: -#endif case X86_INS_STAC: case X86_INS_STGI: op->type = RZ_ANALYSIS_OP_TYPE_MOV; @@ -2466,9 +2448,7 @@ static void anop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int case X86_INS_PCMPGTQ: case X86_INS_PCMPISTRI: case X86_INS_PCMPISTRM: -#if CS_API_MAJOR >= 4 case X86_INS_VPCMPB: -#endif case X86_INS_VPCMPD: case X86_INS_VPCMPEQB: case X86_INS_VPCMPEQD: @@ -2483,15 +2463,11 @@ static void anop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int case X86_INS_VPCMPISTRI: case X86_INS_VPCMPISTRM: case X86_INS_VPCMPQ: -#if CS_API_MAJOR >= 4 case X86_INS_VPCMPUB: -#endif case X86_INS_VPCMPUD: case X86_INS_VPCMPUQ: -#if CS_API_MAJOR >= 4 case X86_INS_VPCMPUW: case X86_INS_VPCMPW: -#endif op->type = RZ_ANALYSIS_OP_TYPE_CMP; op->family = RZ_ANALYSIS_OP_FAMILY_SSE; break; @@ -2727,9 +2703,7 @@ static void anop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int op->stackptr = -regsz; op->cycles = CYCLE_MEM + CYCLE_JMP; break; -#if CS_API_MAJOR >= 4 case X86_INS_UD0: -#endif case X86_INS_UD2: #if CS_API_MAJOR == 4 case X86_INS_UD2B: diff --git a/librz/asm/p/asm_m680x_cs.c b/librz/asm/p/asm_m680x_cs.c index 07c70891f24..6aaa83591f2 100644 --- a/librz/asm/p/asm_m680x_cs.c +++ b/librz/asm/p/asm_m680x_cs.c @@ -5,14 +5,6 @@ #include #include -#if CS_API_MAJOR >= 4 && CS_API_MINOR >= 0 -#define CAPSTONE_HAS_M680X 1 -#else -#define CAPSTONE_HAS_M680X 0 -#endif - -#if CAPSTONE_HAS_M680X - static csh cd = 0; static int m680xmode(const char *str) { @@ -104,16 +96,6 @@ RzAsmPlugin rz_asm_plugin_m680x_cs = { .disassemble = &disassemble, }; -#else -RzAsmPlugin rz_asm_plugin_m680x_cs = { - .name = "m680x", - .desc = "Capstone M680X Disassembler (Not supported)", - .license = "BSD", - .arch = "m680x", - .bits = 8 | 32, -}; -#endif - #ifndef RZ_PLUGIN_INCORE RZ_API RzLibStruct rizin_plugin = { .type = RZ_LIB_TYPE_ASM, diff --git a/librz/asm/p/asm_x86_cs.c b/librz/asm/p/asm_x86_cs.c index 1bd15da809e..b3a1e78541e 100644 --- a/librz/asm/p/asm_x86_cs.c +++ b/librz/asm/p/asm_x86_cs.c @@ -51,13 +51,9 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { } // always unsigned immediates (kernel addresses) // maybe rizin should have an option for this too? -#if CS_API_MAJOR >= 4 cs_option(cd, CS_OPT_UNSIGNED, CS_OPT_ON); -#endif if (a->syntax == RZ_ASM_SYNTAX_MASM) { -#if CS_API_MAJOR >= 4 cs_option(cd, CS_OPT_SYNTAX, CS_OPT_SYNTAX_MASM); -#endif } else if (a->syntax == RZ_ASM_SYNTAX_ATT) { cs_option(cd, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); } else { From 0f2a8ff186283bec8a0ae812aa45865dc4c0e2f1 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 09:21:48 -0500 Subject: [PATCH 06/19] Add CSv5 workflow to CI. --- .github/workflows/ci.yml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4410e47a0f1..3a7e6b56b3d 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -63,6 +63,7 @@ jobs: linux-clang-tests-asan, linux-gcc-tests-codecov, capstone-v4, + capstone-v5, ] include: - name: linux-meson-clang-tests @@ -148,6 +149,16 @@ jobs: timeout: 45 cflags: "-Wno-cpp" allow_failure: true + - name: capstone-v5 + os: ubuntu-22.04 + build_system: meson + compiler: gcc + meson_options: -Dbuildtype=release -Duse_capstone_version=v5 --werror + run_tests: false + enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }} + timeout: 45 + cflags: "-Wno-cpp" + allow_failure: true - name: no-gpl-code os: ubuntu-22.04 build_system: meson From 9a861e96a686b19e6f5b4245ee8f3927709cd7c4 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 11:28:39 -0500 Subject: [PATCH 07/19] Handle ARM pre v6 build errors. --- librz/analysis/arch/arm/arm_accessors32.h | 8 ++ librz/analysis/arch/arm/arm_cs.h | 4 + librz/analysis/arch/arm/arm_esil32.c | 38 +++++--- librz/analysis/arch/arm/arm_il32.c | 91 ++++++++++++++--- librz/analysis/p/analysis_arm_cs.c | 114 +++++++++++++++++----- librz/asm/arch/arm/arm_it.c | 64 ++++++++++++ librz/asm/p/asm_arm_cs.c | 52 ++++++++++ 7 files changed, 318 insertions(+), 53 deletions(-) diff --git a/librz/analysis/arch/arm/arm_accessors32.h b/librz/analysis/arch/arm/arm_accessors32.h index a8669819619..af9ea46bb06 100644 --- a/librz/analysis/arch/arm/arm_accessors32.h +++ b/librz/analysis/arch/arm/arm_accessors32.h @@ -21,7 +21,9 @@ #define MEMDISP_BV(x) (HASMEMINDEX(x) ? REG_VAL(insn->detail->arm.operands[x].mem.index) : U32(MEMDISP(x))) #define ISIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_IMM || insn->detail->arm.operands[x].type == ARM_OP_FP) #define ISREG(x) (insn->detail->arm.operands[x].type == ARM_OP_REG) +#if CS_NEXT_VERSION >= 6 #define ISPSRFLAGS(x) (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR) +#endif #define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM) #define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP) @@ -39,3 +41,9 @@ #define ISWRITEBACK32() insn->detail->writeback #define ISPREINDEX32() (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())) || \ ((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32()) && (!ISPOSTINDEX()))) + +#if CS_NEXT_VERSION >= 6 +#define CS_ARMCC(CC) ARMCC_##CC +#else +#define CS_ARMCC(CC) ARM_CC_##CC +#endif diff --git a/librz/analysis/arch/arm/arm_cs.h b/librz/analysis/arch/arm/arm_cs.h index efb9e8e5fd7..f93a28abd78 100644 --- a/librz/analysis/arch/arm/arm_cs.h +++ b/librz/analysis/arch/arm/arm_cs.h @@ -12,7 +12,11 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a RZ_IPI bool rz_arm_cs_is_group_member(RZ_NONNULL const cs_insn *insn, arm_insn_group feature); +#if CS_NEXT_VERSION >= 6 RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCodes cond_type); +#else +RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type); +#endif RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type); RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb); diff --git a/librz/analysis/arch/arm/arm_esil32.c b/librz/analysis/arch/arm/arm_esil32.c index 507cc611928..c50c8a33f61 100644 --- a/librz/analysis/arch/arm/arm_esil32.c +++ b/librz/analysis/arch/arm/arm_esil32.c @@ -59,72 +59,76 @@ static unsigned int regsize32(cs_insn *insn, int n) { #define REGSIZE32(x) regsize32(insn, x) +#if CS_NEXT_VERSION >= 6 // return postfix RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCodes cond_type) { +#else +RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type) { +#endif const char *close_cond[2]; close_cond[0] = ""; close_cond[1] = ",}"; int close_type = 0; switch (cond_type) { - case ARMCC_EQ: + case CS_ARMCC(EQ): close_type = 1; rz_strbuf_setf(&op->esil, "zf,?{,"); break; - case ARMCC_NE: + case CS_ARMCC(NE): close_type = 1; rz_strbuf_setf(&op->esil, "zf,!,?{,"); break; - case ARMCC_HS: + case CS_ARMCC(HS): close_type = 1; rz_strbuf_setf(&op->esil, "cf,?{,"); break; - case ARMCC_LO: + case CS_ARMCC(LO): close_type = 1; rz_strbuf_setf(&op->esil, "cf,!,?{,"); break; - case ARMCC_MI: + case CS_ARMCC(MI): close_type = 1; rz_strbuf_setf(&op->esil, "nf,?{,"); break; - case ARMCC_PL: + case CS_ARMCC(PL): close_type = 1; rz_strbuf_setf(&op->esil, "nf,!,?{,"); break; - case ARMCC_VS: + case CS_ARMCC(VS): close_type = 1; rz_strbuf_setf(&op->esil, "vf,?{,"); break; - case ARMCC_VC: + case CS_ARMCC(VC): close_type = 1; rz_strbuf_setf(&op->esil, "vf,!,?{,"); break; - case ARMCC_HI: + case CS_ARMCC(HI): close_type = 1; rz_strbuf_setf(&op->esil, "cf,zf,!,&,?{,"); break; - case ARMCC_LS: + case CS_ARMCC(LS): close_type = 1; rz_strbuf_setf(&op->esil, "cf,!,zf,|,?{,"); break; - case ARMCC_GE: + case CS_ARMCC(GE): close_type = 1; rz_strbuf_setf(&op->esil, "nf,vf,^,!,?{,"); break; - case ARMCC_LT: + case CS_ARMCC(LT): close_type = 1; rz_strbuf_setf(&op->esil, "nf,vf,^,?{,"); break; - case ARMCC_GT: + case CS_ARMCC(GT): // zf == 0 && nf == vf close_type = 1; rz_strbuf_setf(&op->esil, "zf,!,nf,vf,^,!,&,?{,"); break; - case ARMCC_LE: + case CS_ARMCC(LE): // zf == 1 || nf != vf close_type = 1; rz_strbuf_setf(&op->esil, "zf,nf,vf,^,|,?{,"); break; - case ARMCC_AL: + case CS_ARMCC(AL): // always executed break; default: @@ -844,7 +848,11 @@ r6,r5,r4,3,sp,[*],12,sp,+= // TODO: esil for MRS break; case ARM_INS_MSR: +#if CS_NEXT_VERSION >= 6 msr_flags = insn->detail->arm.operands[0].sysop.msr_mask; +#else + msr_flags = insn->detail->arm.operands[0].reg >> 4; +#endif rz_strbuf_appendf(&op->esil, "0,"); if (msr_flags & 1) { rz_strbuf_appendf(&op->esil, "0xFF,|,"); diff --git a/librz/analysis/arch/arm/arm_il32.c b/librz/analysis/arch/arm/arm_il32.c index e3fca1a1b2e..82b81b103bc 100644 --- a/librz/analysis/arch/arm/arm_il32.c +++ b/librz/analysis/arch/arm/arm_il32.c @@ -302,37 +302,41 @@ static RzILOpEffect *write_reg(arm_reg reg, RZ_OWN RZ_NONNULL RzILOpBitVector *v * IL for arm condition * unconditional is returned as NULL (rather than true), for simpler code */ +#if CS_NEXT_VERSION >= 6 static RZ_NULLABLE RzILOpBool *cond(ARMCC_CondCodes c) { +#else +static RZ_NULLABLE RzILOpBool *cond(arm_cc c) { +#endif switch (c) { - case ARMCC_EQ: + case CS_ARMCC(EQ): return VARG("zf"); - case ARMCC_NE: + case CS_ARMCC(NE): return INV(VARG("zf")); - case ARMCC_HS: + case CS_ARMCC(HS): return VARG("cf"); - case ARMCC_LO: + case CS_ARMCC(LO): return INV(VARG("cf")); - case ARMCC_MI: + case CS_ARMCC(MI): return VARG("nf"); - case ARMCC_PL: + case CS_ARMCC(PL): return INV(VARG("nf")); - case ARMCC_VS: + case CS_ARMCC(VS): return VARG("vf"); - case ARMCC_VC: + case CS_ARMCC(VC): return INV(VARG("vf")); - case ARMCC_HI: + case CS_ARMCC(HI): return AND(VARG("cf"), INV(VARG("zf"))); - case ARMCC_LS: + case CS_ARMCC(LS): return OR(INV(VARG("cf")), VARG("zf")); - case ARMCC_GE: + case CS_ARMCC(GE): return INV(XOR(VARG("nf"), VARG("vf"))); - case ARMCC_LT: + case CS_ARMCC(LT): return XOR(VARG("nf"), VARG("vf")); - case ARMCC_GT: + case CS_ARMCC(GT): return AND(INV(VARG("zf")), INV(XOR(VARG("nf"), VARG("vf")))); - case ARMCC_LE: + case CS_ARMCC(LE): return OR(VARG("zf"), XOR(VARG("nf"), VARG("vf"))); - case ARMCC_AL: + case CS_ARMCC(AL): default: return NULL; } @@ -1470,6 +1474,7 @@ static RzILOpEffect *mla(cs_insn *insn, bool is_thumb) { * ARM: mrs */ static RzILOpEffect *mrs(cs_insn *insn, bool is_thumb) { +#if CS_NEXT_VERSION >= 6 if (!ISREG(0) || !(ISREG(1) || ISPSRFLAGS(1))) { return NULL; } @@ -1477,6 +1482,15 @@ static RzILOpEffect *mrs(cs_insn *insn, bool is_thumb) { // only these regs supported return NULL; } +#else + if (!ISREG(0) || !(ISREG(1))) { + return NULL; + } + if (REGID(1) != ARM_REG_CPSR && REGID(1) != ARM_REG_SPSR && REGID(1) != ARM_REG_APSR) { + // only these regs supported + return NULL; + } +#endif // There are more bits in ARM, but this is all we have: return write_reg(REGID(0), LOGOR(ITE(VARG("nf"), U32(1ul << 31), U32(0)), @@ -1493,6 +1507,7 @@ static RzILOpEffect *mrs(cs_insn *insn, bool is_thumb) { */ static RzILOpEffect *msr(cs_insn *insn, bool is_thumb) { cs_arm_op *dst = &insn->detail->arm.operands[0]; +#if CS_NEXT_VERSION >= 6 if ((dst->type != ARM_OP_SYSREG) && (dst->type != ARM_OP_CPSR) && (dst->type != ARM_OP_SPSR)) { return NULL; } @@ -1515,6 +1530,30 @@ static RzILOpEffect *msr(cs_insn *insn, bool is_thumb) { update_s = (dst->sysop.psr_bits & ARM_FIELD_CPSR_S) || (dst->sysop.psr_bits & ARM_FIELD_SPSR_S); break; } +#else + if (dst->type != ARM_OP_SYSREG) { + return NULL; + } + // check if the reg+mask contains any of the flags we have: + bool update_f = false; + bool update_s = false; + switch (dst->reg) { + case ARM_SYSREG_APSR_NZCVQ: + update_f = true; + break; + case ARM_SYSREG_APSR_G: + update_s = true; + break; + case ARM_SYSREG_APSR_NZCVQG: + update_f = true; + update_s = true; + break; + default: + update_f = (dst->reg & ARM_SYSREG_CPSR_F) || (dst->reg & ARM_SYSREG_SPSR_F); + update_s = (dst->reg & ARM_SYSREG_CPSR_S) || (dst->reg & ARM_SYSREG_SPSR_S); + break; + } +#endif if (!update_f && !update_s) { // no flags we know return NULL; @@ -3537,7 +3576,11 @@ static RzILOpEffect *try_as_int_cvt(cs_insn *insn, bool is_thumb, bool *success) bv_sz = cvt_isize(VVEC_DT(insn), &is_signed); ut32 fl_sz = rz_float_get_format_info(is_f2i ? from_fmt : to_fmt, RZ_FLOAT_INFO_TOTAL_LEN); +#if CS_NEXT_VERSION >= 6 if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) { +#else + if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) { +#endif // vfp // VCVT.F64.S32/U32
, // VCVT.F32.S32/U32 , @@ -3770,7 +3813,11 @@ static RzILOpEffect *vadd(cs_insn *insn, bool is_thumb) { RzFloatFormat fmt = dt2fmt(dt); bool is_float_vec = fmt == RZ_FLOAT_UNK ? false : true; +#if CS_NEXT_VERSION >= 6 if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) { +#else + if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) { +#endif // VFP return write_reg(REGID(0), F2BV(FADD(RZ_FLOAT_RMODE_RNE, @@ -3817,7 +3864,11 @@ static RzILOpEffect *vsub(cs_insn *insn, bool is_thumb) { RzFloatFormat fmt = dt2fmt(dt); bool is_float_vec = fmt == RZ_FLOAT_UNK ? false : true; +#if CS_NEXT_VERSION >= 6 if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) { +#else + if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) { +#endif // VFP return write_reg(REGID(0), F2BV(FSUB(RZ_FLOAT_RMODE_RNE, @@ -3862,7 +3913,11 @@ static RzILOpEffect *vmul(cs_insn *insn, bool is_thumb) { arm_vectordata_type dt = VVEC_DT(insn); RzFloatFormat fmt = dt2fmt(dt); +#if CS_NEXT_VERSION >= 6 if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) { +#else + if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) { +#endif // VFP fmul return write_reg(REGID(0), F2BV(FMUL(RZ_FLOAT_RMODE_RNE, @@ -3959,7 +4014,11 @@ static RzILOpEffect *vabs(cs_insn *insn, bool is_thumb) { return NULL; } - if (rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) { +#if CS_NEXT_VERSION >= 6 + if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) { +#else + if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) { +#endif // not implement return NULL; } diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index 4ddf6ccfeae..250b17acd57 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -13,6 +13,47 @@ #include "../arch/arm/arm_accessors32.h" #include "../arch/arm/arm_accessors64.h" #include "../../asm/arch/arm/arm_it.h" +#include "subprojects/capstone-4.0.2/include/capstone/arm.h" + +#if CS_NEXT_VERSION < 6 +inline static const char *ARMCondCodeToString(arm_cc cc) +{ + switch (cc) { + default: + assert(0 && "Unknown condition code"); + case ARM_CC_EQ: + return "eq"; + case ARM_CC_NE: + return "ne"; + case ARM_CC_HS: + return "hs"; + case ARM_CC_LO: + return "lo"; + case ARM_CC_MI: + return "mi"; + case ARM_CC_PL: + return "pl"; + case ARM_CC_VS: + return "vs"; + case ARM_CC_VC: + return "vc"; + case ARM_CC_HI: + return "hi"; + case ARM_CC_LS: + return "ls"; + case ARM_CC_GE: + return "ge"; + case ARM_CC_LT: + return "lt"; + case ARM_CC_GT: + return "gt"; + case ARM_CC_LE: + return "le"; + case ARM_CC_AL: + return "al"; + } +} +#endif typedef struct arm_cs_context_t { RzArmITContext it; @@ -253,9 +294,15 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { if (x->cps_flag != ARM_CPSFLAG_INVALID) { pj_ki(pj, "cps_flag", x->cps_flag); } +#if CS_NEXT_VERSION >= 6 if (x->cc != ARMCC_UNDEF && x->cc != ARMCC_AL) { pj_ks(pj, "cc", ARMCondCodeToString(x->cc)); } +#else + if (x->cc != ARM_CC_INVALID && x->cc != ARM_CC_AL) { + pj_ks(pj, "cc", ARMCondCodeToString(x->cc)); + } +#endif if (x->mem_barrier != ARM_MB_RESERVED_0) { pj_ki(pj, "mem_barrier", x->mem_barrier - 1); } @@ -515,31 +562,31 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { } static int cond_cs2r2_32(int cc) { - if (cc == ARMCC_AL || cc < 0) { + if (cc == CS_ARMCC(AL) || cc < 0) { cc = RZ_TYPE_COND_AL; } else { switch (cc) { - case ARMCC_EQ: cc = RZ_TYPE_COND_EQ; break; - case ARMCC_NE: cc = RZ_TYPE_COND_NE; break; - case ARMCC_HS: cc = RZ_TYPE_COND_HS; break; - case ARMCC_LO: cc = RZ_TYPE_COND_LO; break; - case ARMCC_MI: cc = RZ_TYPE_COND_MI; break; - case ARMCC_PL: cc = RZ_TYPE_COND_PL; break; - case ARMCC_VS: cc = RZ_TYPE_COND_VS; break; - case ARMCC_VC: cc = RZ_TYPE_COND_VC; break; - case ARMCC_HI: cc = RZ_TYPE_COND_HI; break; - case ARMCC_LS: cc = RZ_TYPE_COND_LS; break; - case ARMCC_GE: cc = RZ_TYPE_COND_GE; break; - case ARMCC_LT: cc = RZ_TYPE_COND_LT; break; - case ARMCC_GT: cc = RZ_TYPE_COND_GT; break; - case ARMCC_LE: cc = RZ_TYPE_COND_LE; break; + case CS_ARMCC(EQ): cc = RZ_TYPE_COND_EQ; break; + case CS_ARMCC(NE): cc = RZ_TYPE_COND_NE; break; + case CS_ARMCC(HS): cc = RZ_TYPE_COND_HS; break; + case CS_ARMCC(LO): cc = RZ_TYPE_COND_LO; break; + case CS_ARMCC(MI): cc = RZ_TYPE_COND_MI; break; + case CS_ARMCC(PL): cc = RZ_TYPE_COND_PL; break; + case CS_ARMCC(VS): cc = RZ_TYPE_COND_VS; break; + case CS_ARMCC(VC): cc = RZ_TYPE_COND_VC; break; + case CS_ARMCC(HI): cc = RZ_TYPE_COND_HI; break; + case CS_ARMCC(LS): cc = RZ_TYPE_COND_LS; break; + case CS_ARMCC(GE): cc = RZ_TYPE_COND_GE; break; + case CS_ARMCC(LT): cc = RZ_TYPE_COND_LT; break; + case CS_ARMCC(GT): cc = RZ_TYPE_COND_GT; break; + case CS_ARMCC(LE): cc = RZ_TYPE_COND_LE; break; } } return cc; } static int cond_cs2r2_64(int cc) { - if (cc == ARMCC_AL || cc < 0) { + if (cc == ARM64_CC_AL || cc < 0) { cc = RZ_TYPE_COND_AL; } else { switch (cc) { @@ -887,7 +934,7 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } if (REGID(0) == ARM_REG_PC) { op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - if (insn->detail->arm.cc != ARMCC_AL) { + if (insn->detail->arm.cc != CS_ARMCC(AL)) { // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; } @@ -1012,7 +1059,9 @@ static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, b return; } op->cycles = 1; + /* grab family */ +#if CS_NEXT_VERSION >= 6 if (cs_insn_group(handle, insn, ARM_FEATURE_HasAES)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasCRC)) { @@ -1031,6 +1080,21 @@ static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, b } else { op->family = RZ_ANALYSIS_OP_FAMILY_CPU; } +#else + if (cs_insn_group(handle, insn, ARM64_GRP_CRYPTO)) { + op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; + } else if (cs_insn_group(handle, insn, ARM64_GRP_CRC)) { + op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; + } else if (cs_insn_group(handle, insn, ARM64_GRP_PRIVILEGE)) { + op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; + } else if (cs_insn_group(handle, insn, ARM64_GRP_NEON)) { + op->family = RZ_ANALYSIS_OP_FAMILY_MMX; + } else if (cs_insn_group(handle, insn, ARM64_GRP_FPARMV8)) { + op->family = RZ_ANALYSIS_OP_FAMILY_FPU; + } else { + op->family = RZ_ANALYSIS_OP_FAMILY_CPU; + } +#endif if (insn->id != ARM_INS_IT) { rz_arm_it_update_nonblock(&ctx->it, insn); @@ -1097,7 +1161,7 @@ jmp $$ + 4 + ( [delta] * 2 ) for (i = 0; i < insn->detail->arm.op_count; i++) { if (insn->detail->arm.operands[i].type == ARM_OP_REG && insn->detail->arm.operands[i].reg == ARM_REG_PC) { - if (insn->detail->arm.cc == ARMCC_AL) { + if (insn->detail->arm.cc == CS_ARMCC(AL)) { op->type = RZ_ANALYSIS_OP_TYPE_RET; } else { op->type = RZ_ANALYSIS_OP_TYPE_CRET; @@ -1142,7 +1206,7 @@ jmp $$ + 4 + ( [delta] * 2 ) op->type = RZ_ANALYSIS_OP_TYPE_ADD; if (REGID(0) == ARM_REG_PC) { op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - if (REGID(1) == ARM_REG_PC && insn->detail->arm.cc != ARMCC_AL) { + if (REGID(1) == ARM_REG_PC && insn->detail->arm.cc != CS_ARMCC(AL)) { // op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; op->fail = addr + op->size; @@ -1325,7 +1389,7 @@ jmp $$ + 4 + ( [delta] * 2 ) op->disp = MEMDISP(1); if (REGID(0) == ARM_REG_PC) { op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - if (insn->detail->arm.cc != ARMCC_AL) { + if (insn->detail->arm.cc != CS_ARMCC(AL)) { // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; } @@ -1348,7 +1412,7 @@ jmp $$ + 4 + ( [delta] * 2 ) } else if (REGBASE(1) == ARM_REG_PC) { op->ptr = (addr & ~3LL) + (thumb ? 4 : 8) + MEMDISP(1); op->refptr = 4; - if (REGID(0) == ARM_REG_PC && insn->detail->arm.cc != ARMCC_AL) { + if (REGID(0) == ARM_REG_PC && insn->detail->arm.cc != CS_ARMCC(AL)) { // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; op->fail = addr + op->size; @@ -1401,10 +1465,14 @@ jmp $$ + 4 + ( [delta] * 2 ) case ARM_INS_B: /* b.cc label */ op->cycles = 4; +#if CS_NEXT_VERSION >= 6 if (insn->detail->arm.cc == ARMCC_UNDEF) { +#else + if (insn->detail->arm.cc == ARM_CC_INVALID) { +#endif op->type = RZ_ANALYSIS_OP_TYPE_ILL; op->fail = addr + op->size; - } else if (insn->detail->arm.cc == ARMCC_AL) { + } else if (insn->detail->arm.cc == CS_ARMCC(AL)) { op->type = RZ_ANALYSIS_OP_TYPE_JMP; op->fail = UT64_MAX; } else { @@ -1740,7 +1808,9 @@ static int analysis_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *bu if (ctx->handle == 0) { ret = (a->bits == 64) ? cs_open(CS_ARCH_ARM64, mode, &ctx->handle) : cs_open(CS_ARCH_ARM, mode, &ctx->handle); cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_ON); +#if CS_NEXT_VERSION >= 6 cs_option(ctx->handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS); +#endif if (ret != CS_ERR_OK) { ctx->handle = 0; return -1; diff --git a/librz/asm/arch/arm/arm_it.c b/librz/asm/arch/arm/arm_it.c index 9c326c20a1f..15951d0361b 100644 --- a/librz/asm/arch/arm/arm_it.c +++ b/librz/asm/arch/arm/arm_it.c @@ -28,13 +28,56 @@ RZ_API void rz_arm_it_context_fini(RzArmITContext *ctx) { ht_uu_free(ctx->ht_itcond); } +#if CS_NEXT_VERSION < 6 +inline static arm_cc ARMCC_getOppositeCondition(arm_cc cc) +{ + switch (cc) { + default: + // llvm_unreachable("Unknown condition code"); + assert(0); + case ARM_CC_EQ: + return ARM_CC_NE; + case ARM_CC_NE: + return ARM_CC_EQ; + case ARM_CC_HS: + return ARM_CC_LO; + case ARM_CC_LO: + return ARM_CC_HS; + case ARM_CC_MI: + return ARM_CC_PL; + case ARM_CC_PL: + return ARM_CC_MI; + case ARM_CC_VS: + return ARM_CC_VC; + case ARM_CC_VC: + return ARM_CC_VS; + case ARM_CC_HI: + return ARM_CC_LS; + case ARM_CC_LS: + return ARM_CC_HI; + case ARM_CC_GE: + return ARM_CC_LT; + case ARM_CC_LT: + return ARM_CC_GE; + case ARM_CC_GT: + return ARM_CC_LE; + case ARM_CC_LE: + return ARM_CC_GT; + } +} +#endif + /** * Signal a newly detected IT block * \p insn must be ARM_INS_IT */ RZ_API void rz_arm_it_update_block(RzArmITContext *ctx, cs_insn *insn) { +#if CS_NEXT_VERSION >= 6 rz_return_if_fail(ctx && insn && (insn->id == ARM_INS_IT || insn->id == ARM_INS_VPT)); bool is_vpt = insn->id == ARM_INS_VPT; +#else + rz_return_if_fail(ctx && insn && (insn->id == ARM_INS_IT)); +#endif bool found; ht_uu_find(ctx->ht_itblock, insn->address, &found); if (found) { @@ -50,6 +93,7 @@ RZ_API void rz_arm_it_update_block(RzArmITContext *ctx, cs_insn *insn) { ArmCSITCond cond = { 0 }; cond.off = block.off[i - 1] = 2 * i; switch (insn->mnemonic[i]) { +#if CS_NEXT_VERSION >= 6 case 0x74: //'t' cond.cond = is_vpt ? insn->detail->arm.vcc : insn->detail->arm.cc; break; @@ -62,10 +106,26 @@ RZ_API void rz_arm_it_update_block(RzArmITContext *ctx, cs_insn *insn) { cond.cond = ARMCC_getOppositeCondition(insn->detail->arm.cc); } break; +#else + case 0x74: //'t' + cond.cond = insn->detail->arm.cc; + break; + case 0x65: //'e' + if (insn->detail->arm.cc == ARM_CC_AL) { + cond.cond = ARM_CC_AL; + } else { + cond.cond = ARMCC_getOppositeCondition(insn->detail->arm.cc); + } + break; +#endif default: break; } +#if CS_NEXT_VERSION >= 6 cond.vpt = is_vpt ? 1 : 0; +#else + cond.vpt = 0; +#endif RZ_STATIC_ASSERT(sizeof(cond) == sizeof(cond.packed)); ht_uu_update(ctx->ht_itcond, insn->address + cond.off, cond.packed); } @@ -100,11 +160,15 @@ RZ_API bool rz_arm_it_apply_cond(RzArmITContext *ctx, cs_insn *insn) { if (!found) { return false; } +#if CS_NEXT_VERSION >= 6 if (cond.vpt) { insn->detail->arm.vcc = cond.cond; } else { insn->detail->arm.cc = cond.cond; } +#else + insn->detail->arm.cc = cond.cond; +#endif insn->detail->arm.update_flags = 0; // Readjust if we detected that the previous assumption of all-2-byte instructions in diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index 4151d32eb35..cfe2e2fae13 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -16,6 +16,46 @@ typedef struct arm_cs_context_t { int obits; } ArmCSContext; +#if CS_NEXT_VERSION < 6 +inline static const char *ARMCondCodeToString(arm_cc cc) +{ + switch (cc) { + default: + assert(0 && "Unknown condition code"); + case ARM_CC_EQ: + return "eq"; + case ARM_CC_NE: + return "ne"; + case ARM_CC_HS: + return "hs"; + case ARM_CC_LO: + return "lo"; + case ARM_CC_MI: + return "mi"; + case ARM_CC_PL: + return "pl"; + case ARM_CC_VS: + return "vs"; + case ARM_CC_VC: + return "vc"; + case ARM_CC_HI: + return "hi"; + case ARM_CC_LS: + return "ls"; + case ARM_CC_GE: + return "ge"; + case ARM_CC_LT: + return "lt"; + case ARM_CC_GT: + return "gt"; + case ARM_CC_LE: + return "le"; + case ARM_CC_AL: + return "al"; + } +} +#endif + bool arm64ass(const char *str, ut64 addr, ut32 *op); static bool check_features(RzAsm *a, cs_insn *insn) { @@ -27,9 +67,15 @@ static bool check_features(RzAsm *a, cs_insn *insn) { for (i = 0; i < insn->detail->groups_count; i++) { int id = insn->detail->groups[i]; switch (id) { +#if CS_VERSION_NEXT >= 6 case ARM_FEATURE_IsARM: case ARM_FEATURE_IsThumb: case ARM_FEATURE_IsThumb2: +#else + case ARM_GRP_ARM: + case ARM_GRP_THUMB: + case ARM_GRP_THUMB2: +#endif continue; default: if (id < 128) { @@ -92,7 +138,9 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { } } cs_option(ctx->cd, CS_OPT_SYNTAX, (a->syntax == RZ_ASM_SYNTAX_REGNUM) ? CS_OPT_SYNTAX_NOREGNAME : CS_OPT_SYNTAX_DEFAULT); +#if CS_VERSION_NEXT >= 6 cs_option(ctx->cd, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS); +#endif cs_option(ctx->cd, CS_OPT_DETAIL, (a->features && *a->features) ? CS_OPT_ON : CS_OPT_OFF); cs_option(ctx->cd, CS_OPT_DETAIL, CS_OPT_ON); if (!buf) { @@ -119,7 +167,11 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { } if (op && !op->size) { op->size = insn->size; +#if CS_NEXT_VERSION >= 6 if (insn->id == ARM_INS_IT || insn->id == ARM_INS_VPT) { +#else + if (insn->id == ARM_INS_IT) { +#endif rz_arm_it_update_block(&ctx->it, insn); } else { rz_arm_it_update_nonblock(&ctx->it, insn); From 771a885790968636efbfe5428255b2ced4238f1a Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 13:05:54 -0500 Subject: [PATCH 08/19] Fix PPC build errors for CS < v6 --- librz/analysis/arch/ppc/ppc_il.c | 8 ++------ librz/analysis/arch/ppc/ppc_il.h | 2 ++ librz/analysis/arch/ppc/ppc_il_ops.c | 20 ++++++++++++++++++++ librz/analysis/p/analysis_ppc_cs.c | 10 +++++++++- 4 files changed, 33 insertions(+), 7 deletions(-) diff --git a/librz/analysis/arch/ppc/ppc_il.c b/librz/analysis/arch/ppc/ppc_il.c index dd8f1b45cb4..5c47d7a1eca 100644 --- a/librz/analysis/arch/ppc/ppc_il.c +++ b/librz/analysis/arch/ppc/ppc_il.c @@ -267,18 +267,12 @@ RZ_IPI bool ppc_sets_lr(ut32 insn_id) { case PPC_INS_BGEL: case PPC_INS_BGELRL: case PPC_INS_BGELA: - case PPC_INS_BDNZTL: - case PPC_INS_BDNZTLA: case PPC_INS_BDNZL: case PPC_INS_BDNZLA: case PPC_INS_BDNZLRL: case PPC_INS_BDZL: case PPC_INS_BDZLA: case PPC_INS_BDZLRL: - case PPC_INS_BL: - case PPC_INS_BLA: - case PPC_INS_BLRL: - case PPC_INS_BCLA: case PPC_INS_BDNZTL: case PPC_INS_BDNZTLA: case PPC_INS_BDNZFL: @@ -300,6 +294,7 @@ RZ_IPI bool ppc_sets_lr(ut32 insn_id) { } } +#if CS_NEXT_VERSION >= 6 /** * \brief Returns true if the given branch instruction is conditional. * @@ -310,6 +305,7 @@ RZ_IPI bool ppc_insn_is_conditional(const cs_insn *insn) { rz_return_val_if_fail(insn, false); return PPC_DETAIL(insn).bc.pred_cr != PPC_PRED_INVALID || PPC_DETAIL(insn).bc.pred_ctr != PPC_PRED_INVALID; } +#endif /** * \brief Returns true if the given branch instruction is conditional. diff --git a/librz/analysis/arch/ppc/ppc_il.h b/librz/analysis/arch/ppc/ppc_il.h index b603e8ed988..bff9ee544ec 100644 --- a/librz/analysis/arch/ppc/ppc_il.h +++ b/librz/analysis/arch/ppc/ppc_il.h @@ -165,7 +165,9 @@ RZ_IPI bool ppc_is_algebraic(ut32 insn_id); RZ_IPI bool ppc_sets_lr(ut32 insn_id); RZ_IPI bool ppc_insn_sets_lr(const cs_insn *insn); RZ_IPI bool ppc_is_conditional(ut32 insn_id); +#if CS_NEXT_VERSION >= 6 RZ_IPI bool ppc_insn_is_conditional(const cs_insn *insn); +#endif RZ_IPI bool ppc_moves_to_spr(ut32 insn_id); RZ_IPI bool ppc_is_mul_div_d(const ut32 id, const cs_mode mode); RZ_IPI bool ppc_is_mul_div_u(const ut32 id); diff --git a/librz/analysis/arch/ppc/ppc_il_ops.c b/librz/analysis/arch/ppc/ppc_il_ops.c index 7be7b9766dd..58589a436b5 100644 --- a/librz/analysis/arch/ppc/ppc_il_ops.c +++ b/librz/analysis/arch/ppc/ppc_il_ops.c @@ -361,6 +361,7 @@ static RzILOpEffect *add_sub_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, b // I/M/Z Immediate, Minus one, Zero extend, // C/E/S Carry (sets it), Extends (adds carry it), Shift immediate +#if CS_NEXT_VERSION >= 6 // Handle Add alias switch (insn->alias_id) { default: @@ -370,6 +371,7 @@ static RzILOpEffect *add_sub_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, b case PPC_INS_ALIAS_LIS: // RT = SI << 16 return SETG(rT, EXTEND(PPC_ARCH_BITS, APPEND(SN(16, sI), U16(0)))); } +#endif // EXEC switch (id) { @@ -939,14 +941,26 @@ static RzILOpEffect *move_from_to_spr_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_MTCTR: spr_name = "ctr"; break; +#if CS_NEXT_VERSION < 6 + case PPC_INS_MFXER: + case PPC_INS_MTXER: + if (id == PPC_INS_MTXER) { + return ppc_set_xer(VARG(rS), mode); + } + spr_name = "xer"; + set_val = SETL("val", ppc_get_xer(mode)); + break; +#endif case PPC_INS_MFSPR: case PPC_INS_MTSPR: { +#if CS_NEXT_VERSION >= 6 if (insn->alias_id == PPC_INS_ALIAS_MTXER) { return ppc_set_xer(VARG(rS), mode); } else if (insn->alias_id == PPC_INS_ALIAS_MFXER) { set_val = SETL("val", ppc_get_xer(mode)); break; } +#endif ut32 spr = INSOP(1).imm; switch (spr) { default: @@ -1028,6 +1042,7 @@ static RzILOpEffect *move_from_to_spr_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_MFPID: case PPC_INS_MFTBLO: case PPC_INS_MFTBHI: +#if CS_NEXT_VERSION >= 6 case PPC_INS_MFDBATU0: case PPC_INS_MFDBATL0: case PPC_INS_MFDBATU1: @@ -1044,6 +1059,7 @@ static RzILOpEffect *move_from_to_spr_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_MFIBATL2: case PPC_INS_MFIBATU3: case PPC_INS_MFIBATL3: +#endif case PPC_INS_MFDBATU: case PPC_INS_MFDBATL: case PPC_INS_MFIBATU: @@ -1068,6 +1084,7 @@ static RzILOpEffect *move_from_to_spr_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_MTTBU: case PPC_INS_MTTBLO: case PPC_INS_MTTBHI: +#if CS_NEXT_VERSION >= 6 case PPC_INS_MTDBATU0: case PPC_INS_MTDBATL0: case PPC_INS_MTDBATU1: @@ -1084,6 +1101,7 @@ static RzILOpEffect *move_from_to_spr_op(RZ_BORROW csh handle, RZ_BORROW cs_insn case PPC_INS_MTIBATL2: case PPC_INS_MTIBATU3: case PPC_INS_MTIBATL3: +#endif case PPC_INS_MTDBATU: case PPC_INS_MTDBATL: case PPC_INS_MTIBATU: @@ -1570,10 +1588,12 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn #endif case PPC_INS_XOR: case PPC_INS_XORI: +#if CS_NEXT_VERSION >= 6 if (insn->is_alias && insn->alias_id == PPC_INS_ALIAS_XNOP) { return NOP(); } // fallthrough +#endif case PPC_INS_XORIS: case PPC_INS_EQV: case PPC_INS_EXTSB: diff --git a/librz/analysis/p/analysis_ppc_cs.c b/librz/analysis/p/analysis_ppc_cs.c index cf118f94c8a..8e3a40fcb32 100644 --- a/librz/analysis/p/analysis_ppc_cs.c +++ b/librz/analysis/p/analysis_ppc_cs.c @@ -956,7 +956,9 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf return -1; } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); +#if CS_NEXT_VERSION >= 6 cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL); +#endif } op->size = 4; @@ -1459,7 +1461,13 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf esilprintf(op, "3,%s,&,", cs_reg_name(handle, insn->detail->ppc.bc.crX)); #else case PPC_BC_LE: - esilprintf(op, "3,%s,&,", cs_reg_name(handle, insn->detail->ppc.bc.crX)); + /* 0b01 == equal + * 0b10 == less than */ + if (ARG(1)[0] == '\0') { + esilprintf(op, "3,cr0,&,?{,%s,pc,=,},", ARG(0)); + } else { + esilprintf(op, "3,%s,&,?{,%s,pc,=,},", ARG(0), ARG(1)); + } #endif break; #if CS_NEXT_VERSION >= 6 From cb0fec5a4cf937a0bcd39e394cff9887a944e6e1 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 13:11:41 -0500 Subject: [PATCH 09/19] Fix correct macro name --- librz/asm/p/asm_arm_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index cfe2e2fae13..94140ef1b99 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -67,7 +67,7 @@ static bool check_features(RzAsm *a, cs_insn *insn) { for (i = 0; i < insn->detail->groups_count; i++) { int id = insn->detail->groups[i]; switch (id) { -#if CS_VERSION_NEXT >= 6 +#if CS_NEXT_VERSION >= 6 case ARM_FEATURE_IsARM: case ARM_FEATURE_IsThumb: case ARM_FEATURE_IsThumb2: From 9310c02270d9286c2d681f45434be11054e93ef7 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 13:12:51 -0500 Subject: [PATCH 10/19] Remove wrong include. --- librz/analysis/p/analysis_arm_cs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index 250b17acd57..7078e15df4e 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -13,7 +13,6 @@ #include "../arch/arm/arm_accessors32.h" #include "../arch/arm/arm_accessors64.h" #include "../../asm/arch/arm/arm_it.h" -#include "subprojects/capstone-4.0.2/include/capstone/arm.h" #if CS_NEXT_VERSION < 6 inline static const char *ARMCondCodeToString(arm_cc cc) From 3b6223ebca40225934f3006ca6bc2750b59af369 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 13:17:51 -0500 Subject: [PATCH 11/19] Fix fallthrough warning --- librz/analysis/arch/ppc/ppc_il_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/librz/analysis/arch/ppc/ppc_il_ops.c b/librz/analysis/arch/ppc/ppc_il_ops.c index 58589a436b5..6d14f9e9037 100644 --- a/librz/analysis/arch/ppc/ppc_il_ops.c +++ b/librz/analysis/arch/ppc/ppc_il_ops.c @@ -1592,8 +1592,8 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn if (insn->is_alias && insn->alias_id == PPC_INS_ALIAS_XNOP) { return NOP(); } - // fallthrough #endif + // fallthrough case PPC_INS_XORIS: case PPC_INS_EQV: case PPC_INS_EXTSB: From 5c184e84b05a41ef0cbc00ead3c1663715f111e8 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 13:33:06 -0500 Subject: [PATCH 12/19] Fix getter macros for WB and post-fix flags. --- librz/analysis/arch/arm/arm_accessors32.h | 9 ++--- librz/analysis/arch/arm/arm_esil32.c | 48 +++++++++++------------ librz/analysis/arch/arm/arm_il32.c | 44 ++++++++++----------- librz/analysis/p/analysis_arm_cs.c | 4 ++ 4 files changed, 54 insertions(+), 51 deletions(-) diff --git a/librz/analysis/arch/arm/arm_accessors32.h b/librz/analysis/arch/arm/arm_accessors32.h index af9ea46bb06..b44ebfefa25 100644 --- a/librz/analysis/arch/arm/arm_accessors32.h +++ b/librz/analysis/arch/arm/arm_accessors32.h @@ -37,13 +37,12 @@ SHIFTTYPE(x) == ARM_SFT_RRX_REG) #define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value -#define ISPOSTINDEX() insn->detail->arm.post_index -#define ISWRITEBACK32() insn->detail->writeback -#define ISPREINDEX32() (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())) || \ - ((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32()) && (!ISPOSTINDEX()))) - #if CS_NEXT_VERSION >= 6 #define CS_ARMCC(CC) ARMCC_##CC +#define ISWRITEBACK32() insn->detail->writeback +#define ISPOSTINDEX32() insn->detail->arm.post_index #else #define CS_ARMCC(CC) ARM_CC_##CC +#define ISWRITEBACK32() insn->detail->arm.writeback +#define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32()))) #endif diff --git a/librz/analysis/arch/arm/arm_esil32.c b/librz/analysis/arch/arm/arm_esil32.c index c50c8a33f61..c11cb3958eb 100644 --- a/librz/analysis/arch/arm/arm_esil32.c +++ b/librz/analysis/arch/arm/arm_esil32.c @@ -395,7 +395,7 @@ PUSH { r4, r5, r6, r7, lr } rz_strbuf_appendf(&op->esil, "%s,%s,%d,+,=[4],", REG(i), ARG(0), (i + offset) * 4); } - if (insn->detail->writeback == true) { // writeback, reg should be incremented + if (ISWRITEBACK32() == true) { // writeback, reg should be incremented rz_strbuf_appendf(&op->esil, "%d,%s,+=,", direction * (insn->detail->arm.op_count - 1) * 4, ARG(0)); } @@ -410,7 +410,7 @@ PUSH { r4, r5, r6, r7, lr } width += REGSIZE32(i); } // increment if writeback - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0)); } break; @@ -434,7 +434,7 @@ PUSH { r4, r5, r6, r7, lr } width += REGSIZE32(i); } // increment if writeback - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0)); } break; @@ -493,7 +493,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= for (i = 1; i < insn->detail->arm.op_count; i++) { rz_strbuf_appendf(&op->esil, "%s,%d,+,[4],%s,=,", ARG(0), (i + offset) * 4, REG(i)); } - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, "%d,%s,+=,", direction * (insn->detail->arm.op_count - 1) * 4, ARG(0)); } @@ -549,14 +549,14 @@ r6,r5,r4,3,sp,[*],12,sp,+= default: str_ldr_bytes = 4; } - if (!ISPOSTINDEX()) { + if (!ISPOSTINDEX32()) { if (ISMEM(1) && !HASMEMINDEX(1)) { int disp = MEMDISP(1); char sign = disp >= 0 ? '+' : '-'; disp = disp >= 0 ? disp : -disp; rz_strbuf_appendf(&op->esil, "%s,0x%x,%s,%c,0xffffffff,&,=[%d]", REG(0), disp, MEMBASE(1), sign, str_ldr_bytes); - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=", disp, MEMBASE(1), sign, MEMBASE(1)); } @@ -567,7 +567,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_LSL: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,<<,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->writeback) { // e.g. 'str r2, [r3, r1, lsl 4]!' + if (ISWRITEBACK32()) { // e.g. 'str r2, [r3, r1, lsl 4]!' rz_strbuf_appendf(&op->esil, ",%s,%d,%s,<<,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -575,7 +575,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_LSR: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -583,7 +583,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_ASR: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>>,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>>,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -591,7 +591,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_ROR: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -606,14 +606,14 @@ r6,r5,r4,3,sp,[*],12,sp,+= } else { // No shift rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,0xffffffff,&,=[%d]", REG(0), MEMINDEX(1), MEMBASE(1), str_ldr_bytes); - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%s,%s,+,%s,=", MEMINDEX(1), MEMBASE(1), MEMBASE(1)); } } } } - if (ISPOSTINDEX()) { // e.g. 'str r2, [r3], 4 + if (ISPOSTINDEX32()) { // e.g. 'str r2, [r3], 4 if (!HASMEMINDEX(1) && (str_ldr_bytes != 8)) { // e.g. 'str r2, [r3], 4 rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%d,%s,+=", REG(0), MEMBASE(1), str_ldr_bytes, MEMDISP(1), MEMBASE(1)); @@ -654,7 +654,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= disp = disp >= 0 ? disp : -disp; rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[4],%s,4,%s,+,0xffffffff,&,=[4]", REG(0), MEMBASE(2), REG(1), MEMBASE(2)); - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=", disp, MEMBASE(2), sign, MEMBASE(2)); } @@ -664,7 +664,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= } else { rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[4],%s,4,%s,+,0xffffffff,&,=[4]", REG(0), MEMBASE(2), REG(1), MEMBASE(2)); - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { const char sign = ISMEMINDEXSUB(2) ? '-' : '+'; rz_strbuf_appendf(&op->esil, ",%s,%s,%c=", MEMINDEX(2), MEMBASE(2), sign); @@ -687,7 +687,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",2,2,%s,%d,+,>>,<<,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=", (ut64)MEMDISP(2), pc, pcdelta, REG(0), REG(1)); } else { - int disp = ISPOSTINDEX() ? 0 : MEMDISP(2); + int disp = ISPOSTINDEX32() ? 0 : MEMDISP(2); // not refptr, because we can't grab the reg value statically op->refptr = 4; rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",%s,-,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=", (ut64)-disp, MEMBASE(2), REG(0), REG(1)); @@ -708,16 +708,16 @@ r6,r5,r4,3,sp,[*],12,sp,+= } else { if (HASMEMINDEX(2)) { // e.g. `ldrd r2, r3 [r4, r1]` or `ldrd r2, r3 [r4], r1` const char op_index = ISMEMINDEXSUB(2) ? '-' : '+'; - const char *mem_index = ISPOSTINDEX() ? "0" : MEMINDEX(2); + const char *mem_index = ISPOSTINDEX32() ? "0" : MEMINDEX(2); rz_strbuf_appendf(&op->esil, "%s,%s,%c,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=", mem_index, MEMBASE(2), op_index, REG(0), REG(1)); } else { - int disp = ISPOSTINDEX() ? 0 : MEMDISP(2); + int disp = ISPOSTINDEX32() ? 0 : MEMDISP(2); rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=", disp, MEMBASE(2), REG(0), REG(1)); } - if (insn->detail->writeback) { - if (ISPOSTINDEX()) { + if (ISWRITEBACK32()) { + if (ISPOSTINDEX32()) { if (!HASMEMINDEX(2)) { rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=", MEMBASE(2), MEMDISP(2), MEMBASE(2)); @@ -726,7 +726,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= rz_strbuf_appendf(&op->esil, ",%s,%s,%c,%s,=", MEMINDEX(2), MEMBASE(2), op_index, MEMBASE(2)); } - } else if (ISPREINDEX32()) { + } else { if (HASMEMINDEX(2)) { const char op_index = ISMEMINDEXSUB(2) ? '-' : '+'; rz_strbuf_appendf(&op->esil, ",%s,%s,%c,%s,=", @@ -749,9 +749,9 @@ r6,r5,r4,3,sp,[*],12,sp,+= MEMINDEX(1), MEMBASE(1), REG(0)); } else { rz_strbuf_appendf(&op->esil, "%s,%d,+,[1],%s,=", - MEMBASE(1), ISPOSTINDEX() ? 0 : MEMDISP(1), REG(0)); + MEMBASE(1), ISPOSTINDEX32() ? 0 : MEMDISP(1), REG(0)); } - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=", MEMBASE(1), MEMDISP(1), MEMBASE(1)); } @@ -830,14 +830,14 @@ r6,r5,r4,3,sp,[*],12,sp,+= } else if (HASMEMINDEX(1)) { // e.g. `ldr r2, [r3, r1]` rz_strbuf_appendf(&op->esil, "%s,%s,+,0xffffffff,&,[4],0x%x,&,%s,=", MEMINDEX(1), MEMBASE(1), mask, REG(0)); - } else if (ISPOSTINDEX()) { + } else if (ISPOSTINDEX32()) { rz_strbuf_appendf(&op->esil, "%s,0xffffffff,&,[4],0x%x,&,%s,=", MEMBASE(1), mask, REG(0)); } else { rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,[4],0x%x,&,%s,=", MEMDISP(1), MEMBASE(1), mask, REG(0)); } - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=", MEMBASE(1), MEMDISP(1), MEMBASE(1)); } diff --git a/librz/analysis/arch/arm/arm_il32.c b/librz/analysis/arch/arm/arm_il32.c index 82b81b103bc..66a166cb2db 100644 --- a/librz/analysis/arch/arm/arm_il32.c +++ b/librz/analysis/arch/arm/arm_il32.c @@ -829,10 +829,10 @@ static RzILOpEffect *ldr(cs_insn *insn, bool is_thumb) { if (!addr) { return NULL; } - bool writeback = insn->detail->writeback; + bool writeback = ISWRITEBACK32(); RzILOpEffect *writeback_eff = NULL; - bool writeback_post = insn->detail->arm.post_index; + bool writeback_post = ISPOSTINDEX32(); if (writeback) { arm_reg base = insn->detail->arm.operands[mem_idx].mem.base; writeback_eff = write_reg(base, addr); @@ -908,9 +908,9 @@ static RzILOpEffect *str(cs_insn *insn, bool is_thumb) { if (!addr) { return NULL; } - bool writeback = insn->detail->writeback; + bool writeback = ISWRITEBACK32(); RzILOpEffect *writeback_eff = NULL; - bool writeback_post = insn->detail->arm.post_index; + bool writeback_post = ISPOSTINDEX32(); if (writeback) { arm_reg base = insn->detail->arm.operands[mem_idx].mem.base; writeback_eff = write_reg(base, addr); @@ -1211,7 +1211,7 @@ static RzILOpEffect *stm(cs_insn *insn, bool is_thumb) { } op_first = 1; ptr_reg = REGID(0); - writeback = insn->detail->writeback; + writeback = ISWRITEBACK32(); } size_t op_count = OPCOUNT() - op_first; if (!op_count) { @@ -1272,7 +1272,7 @@ static RzILOpEffect *ldm(cs_insn *insn, bool is_thumb) { } op_first = 1; ptr_reg = REGID(0); - writeback = insn->detail->writeback; + writeback = ISWRITEBACK32(); } size_t op_count = OPCOUNT() - op_first; if (!op_count) { @@ -1912,7 +1912,7 @@ static RzILOpEffect *rfe(cs_insn *insn, bool is_thumb) { RzILOpEffect *wb = NULL; bool wordhigher = insn->id == ARM_INS_RFEDA || insn->id == ARM_INS_RFEIB; bool increment = insn->id == ARM_INS_RFEIA || insn->id == ARM_INS_RFEIB; - if (insn->detail->writeback) { + if (ISWRITEBACK32()) { wb = write_reg(REGID(0), increment ? ADD(DUP(base), U32(8)) : SUB(DUP(base), U32(8))); if (!wb) { @@ -3026,12 +3026,12 @@ static RzILOpEffect *vtst(cs_insn *insn, bool is_thumb) { static RzILOpEffect *vldn_multiple_elem(cs_insn *insn, bool is_thumb) { ut32 mem_idx; ut32 regs = 0; - bool wback = insn->detail->writeback; + bool wback = ISWRITEBACK32(); bool use_rm_as_wback_offset = false; ut32 group_sz = insn->id - ARM_INS_VLD1 + 1; // vldn {list}, [Rn], Rm - if (ISPOSTINDEX()) { + if (ISPOSTINDEX32()) { use_rm_as_wback_offset = true; } regs = OPCOUNT() - 1; @@ -3049,7 +3049,7 @@ static RzILOpEffect *vldn_multiple_elem(cs_insn *insn, bool is_thumb) { RzILOpEffect *wback_eff = NULL; RzILOpEffect *eff = EMPTY(); - RzILOpBitVector *addr = ISPOSTINDEX() ? MEMBASE(mem_idx) : ARG(mem_idx); + RzILOpBitVector *addr = ISPOSTINDEX32() ? MEMBASE(mem_idx) : ARG(mem_idx); for (int i = 0; i < n_groups; ++i) { for (int j = 0; j < lanes; ++j) { @@ -3122,7 +3122,7 @@ static RzILOpEffect *vldn_single_lane(cs_insn *insn, bool is_thumb) { bool use_rm_as_wback_offset = false; ut32 regs; // number of regs in {list} - if (ISPOSTINDEX()) { + if (ISPOSTINDEX32()) { use_rm_as_wback_offset = true; } regs = OPCOUNT() - 1; @@ -3135,7 +3135,7 @@ static RzILOpEffect *vldn_single_lane(cs_insn *insn, bool is_thumb) { RzILOpBitVector *data0, *data1, *data2, *data3; RzILOpEffect *eff; - RzILOpBitVector *addr = ISPOSTINDEX() ? MEMBASE(mem_idx) : ARG(mem_idx); + RzILOpBitVector *addr = ISPOSTINDEX32() ? MEMBASE(mem_idx) : ARG(mem_idx); ut32 vreg_idx = 0; ut32 elem_bits = VVEC_SIZE(insn); ut32 elem_bytes = elem_bits / 8; @@ -3187,7 +3187,7 @@ static RzILOpEffect *vldn_single_lane(cs_insn *insn, bool is_thumb) { return NULL; } - bool wback = insn->detail->writeback; + bool wback = ISWRITEBACK32(); RzILOpEffect *wback_eff; if (wback) { RzILOpBitVector *new_offset = use_rm_as_wback_offset ? MEMINDEX(mem_idx) : UN(32, (ut64)elem_bytes * group_sz); @@ -3204,7 +3204,7 @@ static RzILOpEffect *vldn_all_lane(cs_insn *insn, bool is_thumb) { bool use_rm_as_wback_offset = false; ut32 regs; // number of regs in {list} - if (ISPOSTINDEX()) { + if (ISPOSTINDEX32()) { use_rm_as_wback_offset = true; } regs = OPCOUNT() - 1; @@ -3217,7 +3217,7 @@ static RzILOpEffect *vldn_all_lane(cs_insn *insn, bool is_thumb) { RzILOpBitVector *data0 = NULL, *data1 = NULL, *data2 = NULL, *data3 = NULL; RzILOpEffect *eff = NULL; - RzILOpBitVector *addr = ISPOSTINDEX() ? MEMBASE(mem_idx) : ARG(mem_idx); + RzILOpBitVector *addr = ISPOSTINDEX32() ? MEMBASE(mem_idx) : ARG(mem_idx); ut32 elem_bits = VVEC_SIZE(insn); ut32 elem_bytes = elem_bits / 8; ut32 addr_bits = REG_WIDTH(mem_idx); @@ -3271,7 +3271,7 @@ static RzILOpEffect *vldn_all_lane(cs_insn *insn, bool is_thumb) { return NULL; } - bool wback = insn->detail->writeback; + bool wback = ISWRITEBACK32(); RzILOpEffect *wback_eff; if (wback) { RzILOpBitVector *new_offset = use_rm_as_wback_offset ? MEMINDEX(mem_idx) : UN(32, (ut64)elem_bytes * group_sz); @@ -3303,12 +3303,12 @@ static RzILOpEffect *vldn(cs_insn *insn, bool is_thumb) { static RzILOpEffect *vstn_multiple_elem(cs_insn *insn, bool is_thumb) { ut32 mem_idx; ut32 regs = 0; - bool wback = insn->detail->writeback; + bool wback = ISWRITEBACK32(); bool use_rm_as_wback_offset = false; ut32 group_sz = insn->id - ARM_INS_VST1 + 1; // vldn {list}, [Rn], Rm - if (ISPOSTINDEX()) { + if (ISPOSTINDEX32()) { use_rm_as_wback_offset = true; } regs = OPCOUNT() - 1; @@ -3326,7 +3326,7 @@ static RzILOpEffect *vstn_multiple_elem(cs_insn *insn, bool is_thumb) { RzILOpEffect *wback_eff = NULL; RzILOpEffect *eff = EMPTY(), *eff_ = NULL, *eff__ = NULL; - RzILOpBitVector *addr = ISPOSTINDEX() ? MEMBASE(mem_idx) : ARG(mem_idx); + RzILOpBitVector *addr = ISPOSTINDEX32() ? MEMBASE(mem_idx) : ARG(mem_idx); for (int i = 0; i < n_groups; ++i) { for (int j = 0; j < lanes; ++j) { @@ -3395,7 +3395,7 @@ static RzILOpEffect *vstn_from_single_lane(cs_insn *insn, bool is_thumb) { bool use_rm_as_wback_offset = false; ut32 regs; // number of regs in {list} - if (ISPOSTINDEX()) { + if (ISPOSTINDEX32()) { use_rm_as_wback_offset = true; } regs = OPCOUNT() - 1; @@ -3408,7 +3408,7 @@ static RzILOpEffect *vstn_from_single_lane(cs_insn *insn, bool is_thumb) { RzILOpBitVector *data0, *data1, *data2, *data3; RzILOpEffect *eff, *eff_, *eff__; - RzILOpBitVector *addr = ISPOSTINDEX() ? MEMBASE(mem_idx) : ARG(mem_idx); + RzILOpBitVector *addr = ISPOSTINDEX32() ? MEMBASE(mem_idx) : ARG(mem_idx); ut32 vreg_idx = 0; ut32 elem_bits = VVEC_SIZE(insn); ut32 elem_bytes = elem_bits / 8; @@ -3459,7 +3459,7 @@ static RzILOpEffect *vstn_from_single_lane(cs_insn *insn, bool is_thumb) { return NULL; } - bool wback = insn->detail->writeback; + bool wback = ISWRITEBACK32(); RzILOpEffect *wback_eff; if (wback) { RzILOpBitVector *new_offset = use_rm_as_wback_offset ? MEMINDEX(mem_idx) : UN(32, (ut64)elem_bytes * group_sz); diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index 7078e15df4e..a8ab10024e0 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -278,7 +278,11 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { if (x->update_flags) { pj_kb(pj, "update_flags", true); } +#if CS_NEXT_VERSION >= 6 if (insn->detail->writeback) { +#else + if (x->writeback) { +#endif pj_kb(pj, "writeback", true); } if (x->vector_size) { From dadeb30a7b1c8137bc33dc5da3351482f4bc16bd Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 13:39:51 -0500 Subject: [PATCH 13/19] Fix faulty macro name --- librz/asm/p/asm_arm_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index 94140ef1b99..ad0c648461f 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -138,7 +138,7 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { } } cs_option(ctx->cd, CS_OPT_SYNTAX, (a->syntax == RZ_ASM_SYNTAX_REGNUM) ? CS_OPT_SYNTAX_NOREGNAME : CS_OPT_SYNTAX_DEFAULT); -#if CS_VERSION_NEXT >= 6 +#if CS_NEXT_VERSION >= 6 cs_option(ctx->cd, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS); #endif cs_option(ctx->cd, CS_OPT_DETAIL, (a->features && *a->features) ? CS_OPT_ON : CS_OPT_OFF); From b825f5e84aca80ebad23d5ab466bb4fd7de4f13e Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 21 Oct 2023 13:47:38 -0500 Subject: [PATCH 14/19] Run clang-format --- librz/analysis/arch/arm/arm_accessors32.h | 10 ++-- librz/analysis/p/analysis_arm_cs.c | 71 +++++++++++------------ librz/asm/arch/arm/arm_it.c | 69 +++++++++++----------- librz/asm/arch/arm/armass.c | 6 +- librz/asm/p/asm_arm_cs.c | 71 +++++++++++------------ 5 files changed, 112 insertions(+), 115 deletions(-) diff --git a/librz/analysis/arch/arm/arm_accessors32.h b/librz/analysis/arch/arm/arm_accessors32.h index b44ebfefa25..5ded7f07e28 100644 --- a/librz/analysis/arch/arm/arm_accessors32.h +++ b/librz/analysis/arch/arm/arm_accessors32.h @@ -22,10 +22,10 @@ #define ISIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_IMM || insn->detail->arm.operands[x].type == ARM_OP_FP) #define ISREG(x) (insn->detail->arm.operands[x].type == ARM_OP_REG) #if CS_NEXT_VERSION >= 6 -#define ISPSRFLAGS(x) (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR) +#define ISPSRFLAGS(x) (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR) #endif -#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM) -#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP) +#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM) +#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP) #define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift #define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL @@ -38,11 +38,11 @@ #define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value #if CS_NEXT_VERSION >= 6 -#define CS_ARMCC(CC) ARMCC_##CC +#define CS_ARMCC(CC) ARMCC_##CC #define ISWRITEBACK32() insn->detail->writeback #define ISPOSTINDEX32() insn->detail->arm.post_index #else -#define CS_ARMCC(CC) ARM_CC_##CC +#define CS_ARMCC(CC) ARM_CC_##CC #define ISWRITEBACK32() insn->detail->arm.writeback #define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32()))) #endif diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index a8ab10024e0..838eb342076 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -15,42 +15,41 @@ #include "../../asm/arch/arm/arm_it.h" #if CS_NEXT_VERSION < 6 -inline static const char *ARMCondCodeToString(arm_cc cc) -{ - switch (cc) { - default: - assert(0 && "Unknown condition code"); - case ARM_CC_EQ: - return "eq"; - case ARM_CC_NE: - return "ne"; - case ARM_CC_HS: - return "hs"; - case ARM_CC_LO: - return "lo"; - case ARM_CC_MI: - return "mi"; - case ARM_CC_PL: - return "pl"; - case ARM_CC_VS: - return "vs"; - case ARM_CC_VC: - return "vc"; - case ARM_CC_HI: - return "hi"; - case ARM_CC_LS: - return "ls"; - case ARM_CC_GE: - return "ge"; - case ARM_CC_LT: - return "lt"; - case ARM_CC_GT: - return "gt"; - case ARM_CC_LE: - return "le"; - case ARM_CC_AL: - return "al"; - } +inline static const char *ARMCondCodeToString(arm_cc cc) { + switch (cc) { + default: + assert(0 && "Unknown condition code"); + case ARM_CC_EQ: + return "eq"; + case ARM_CC_NE: + return "ne"; + case ARM_CC_HS: + return "hs"; + case ARM_CC_LO: + return "lo"; + case ARM_CC_MI: + return "mi"; + case ARM_CC_PL: + return "pl"; + case ARM_CC_VS: + return "vs"; + case ARM_CC_VC: + return "vc"; + case ARM_CC_HI: + return "hi"; + case ARM_CC_LS: + return "ls"; + case ARM_CC_GE: + return "ge"; + case ARM_CC_LT: + return "lt"; + case ARM_CC_GT: + return "gt"; + case ARM_CC_LE: + return "le"; + case ARM_CC_AL: + return "al"; + } } #endif diff --git a/librz/asm/arch/arm/arm_it.c b/librz/asm/arch/arm/arm_it.c index 15951d0361b..126e71236d4 100644 --- a/librz/asm/arch/arm/arm_it.c +++ b/librz/asm/arch/arm/arm_it.c @@ -29,41 +29,40 @@ RZ_API void rz_arm_it_context_fini(RzArmITContext *ctx) { } #if CS_NEXT_VERSION < 6 -inline static arm_cc ARMCC_getOppositeCondition(arm_cc cc) -{ - switch (cc) { - default: - // llvm_unreachable("Unknown condition code"); - assert(0); - case ARM_CC_EQ: - return ARM_CC_NE; - case ARM_CC_NE: - return ARM_CC_EQ; - case ARM_CC_HS: - return ARM_CC_LO; - case ARM_CC_LO: - return ARM_CC_HS; - case ARM_CC_MI: - return ARM_CC_PL; - case ARM_CC_PL: - return ARM_CC_MI; - case ARM_CC_VS: - return ARM_CC_VC; - case ARM_CC_VC: - return ARM_CC_VS; - case ARM_CC_HI: - return ARM_CC_LS; - case ARM_CC_LS: - return ARM_CC_HI; - case ARM_CC_GE: - return ARM_CC_LT; - case ARM_CC_LT: - return ARM_CC_GE; - case ARM_CC_GT: - return ARM_CC_LE; - case ARM_CC_LE: - return ARM_CC_GT; - } +inline static arm_cc ARMCC_getOppositeCondition(arm_cc cc) { + switch (cc) { + default: + // llvm_unreachable("Unknown condition code"); + assert(0); + case ARM_CC_EQ: + return ARM_CC_NE; + case ARM_CC_NE: + return ARM_CC_EQ; + case ARM_CC_HS: + return ARM_CC_LO; + case ARM_CC_LO: + return ARM_CC_HS; + case ARM_CC_MI: + return ARM_CC_PL; + case ARM_CC_PL: + return ARM_CC_MI; + case ARM_CC_VS: + return ARM_CC_VC; + case ARM_CC_VC: + return ARM_CC_VS; + case ARM_CC_HI: + return ARM_CC_LS; + case ARM_CC_LS: + return ARM_CC_HI; + case ARM_CC_GE: + return ARM_CC_LT; + case ARM_CC_LT: + return ARM_CC_GE; + case ARM_CC_GT: + return ARM_CC_LE; + case ARM_CC_LE: + return ARM_CC_GT; + } } #endif diff --git a/librz/asm/arch/arm/armass.c b/librz/asm/arch/arm/armass.c index 76540ea9d7b..29c78ebed23 100644 --- a/librz/asm/arch/arm/armass.c +++ b/librz/asm/arch/arm/armass.c @@ -5813,7 +5813,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) { } ao->o |= ((ret >> 16) & 0xff) << 8; ao->o |= ((ret >> 8) & 0xff) << 16; - ao->o |= ((ret)&0xff) << 24; + ao->o |= ((ret) & 0xff) << 24; } else { RZ_LOG_ERROR("assembler: arm: %s: instruction does not accept a register as argument\n", ops[i].name); return 0; @@ -5839,7 +5839,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) { dst /= 4; ao->o |= ((dst >> 16) & 0xff) << 8; ao->o |= ((dst >> 8) & 0xff) << 16; - ao->o |= ((dst)&0xff) << 24; + ao->o |= ((dst) & 0xff) << 24; return 4; } else { ao->o |= (getreg(ao->a[0]) << 24); @@ -5850,7 +5850,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) { o |= ((n >> 12) & 0xf) << 8; o |= ((n >> 8) & 0xf) << 20; o |= ((n >> 4) & 0xf) << 16; - o |= ((n)&0xf) << 24; + o |= ((n) & 0xf) << 24; ao->o |= o; } break; case TYPE_SWI: diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index ad0c648461f..3098314b421 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -17,42 +17,41 @@ typedef struct arm_cs_context_t { } ArmCSContext; #if CS_NEXT_VERSION < 6 -inline static const char *ARMCondCodeToString(arm_cc cc) -{ - switch (cc) { - default: - assert(0 && "Unknown condition code"); - case ARM_CC_EQ: - return "eq"; - case ARM_CC_NE: - return "ne"; - case ARM_CC_HS: - return "hs"; - case ARM_CC_LO: - return "lo"; - case ARM_CC_MI: - return "mi"; - case ARM_CC_PL: - return "pl"; - case ARM_CC_VS: - return "vs"; - case ARM_CC_VC: - return "vc"; - case ARM_CC_HI: - return "hi"; - case ARM_CC_LS: - return "ls"; - case ARM_CC_GE: - return "ge"; - case ARM_CC_LT: - return "lt"; - case ARM_CC_GT: - return "gt"; - case ARM_CC_LE: - return "le"; - case ARM_CC_AL: - return "al"; - } +inline static const char *ARMCondCodeToString(arm_cc cc) { + switch (cc) { + default: + assert(0 && "Unknown condition code"); + case ARM_CC_EQ: + return "eq"; + case ARM_CC_NE: + return "ne"; + case ARM_CC_HS: + return "hs"; + case ARM_CC_LO: + return "lo"; + case ARM_CC_MI: + return "mi"; + case ARM_CC_PL: + return "pl"; + case ARM_CC_VS: + return "vs"; + case ARM_CC_VC: + return "vc"; + case ARM_CC_HI: + return "hi"; + case ARM_CC_LS: + return "ls"; + case ARM_CC_GE: + return "ge"; + case ARM_CC_LT: + return "lt"; + case ARM_CC_GT: + return "gt"; + case ARM_CC_LE: + return "le"; + case ARM_CC_AL: + return "al"; + } } #endif From 9136bc38083b048f47d48a11b81766ecf3ab70fe Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sun, 22 Oct 2023 10:21:04 -0500 Subject: [PATCH 15/19] Check for all float extensions for vabs. --- librz/analysis/arch/arm/arm_cs.h | 1 + librz/analysis/arch/arm/arm_il32.c | 33 +++++++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/librz/analysis/arch/arm/arm_cs.h b/librz/analysis/arch/arm/arm_cs.h index f93a28abd78..25bd301ffac 100644 --- a/librz/analysis/arch/arm/arm_cs.h +++ b/librz/analysis/arch/arm/arm_cs.h @@ -13,6 +13,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a RZ_IPI bool rz_arm_cs_is_group_member(RZ_NONNULL const cs_insn *insn, arm_insn_group feature); #if CS_NEXT_VERSION >= 6 +RZ_IPI bool rz_arm_cs_is_float_insn(const cs_insn *insn); RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCodes cond_type); #else RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type); diff --git a/librz/analysis/arch/arm/arm_il32.c b/librz/analysis/arch/arm/arm_il32.c index 66a166cb2db..7cfac9769d5 100644 --- a/librz/analysis/arch/arm/arm_il32.c +++ b/librz/analysis/arch/arm/arm_il32.c @@ -3561,6 +3561,37 @@ static inline ut32 cvt_isize(arm_vectordata_type type, bool *is_signed) { } } +#if CS_NEXT_VERSION >= 6 +/** + * \brief Tests if the instruction is part of a float supporting + * group (NEON, VFP MVEFloat...). + * + * \param insn The instruction to test. + * \return true The instruction is a float instruction. + * \return false The instruction is not a float instruction. + */ +RZ_IPI bool rz_arm_cs_is_float_insn(const cs_insn *insn) { + rz_return_val_if_fail(insn && insn->detail, false); + uint32_t i = 0; + arm_insn_group group_it = insn->detail->groups[i]; + while (group_it) { + switch (group_it) { + default: + break; + case ARM_FEATURE_HasNEON: + case ARM_FEATURE_HasVFP2: + case ARM_FEATURE_HasVFP3: + case ARM_FEATURE_HasVFP4: + case ARM_FEATURE_HasDPVFP: + case ARM_FEATURE_HasMVEFloat: + return true; + } + group_it = insn->detail->groups[++i]; + } + return false; +} +#endif + static RzILOpEffect *try_as_int_cvt(cs_insn *insn, bool is_thumb, bool *success) { bool is_f2i = false; bool is_signed = false; @@ -4015,7 +4046,7 @@ static RzILOpEffect *vabs(cs_insn *insn, bool is_thumb) { } #if CS_NEXT_VERSION >= 6 - if (!rz_arm_cs_is_group_member(insn, ARM_FEATURE_HasNEON)) { + if (!rz_arm_cs_is_float_insn(insn)) { #else if (!rz_arm_cs_is_group_member(insn, ARM_GRP_NEON)) { #endif From e9ae8c0e20207bed830692e5a242836565deb406 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sun, 22 Oct 2023 12:32:29 -0500 Subject: [PATCH 16/19] Revert clang-format-18 formatting --- librz/asm/arch/arm/armass.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/librz/asm/arch/arm/armass.c b/librz/asm/arch/arm/armass.c index 29c78ebed23..76540ea9d7b 100644 --- a/librz/asm/arch/arm/armass.c +++ b/librz/asm/arch/arm/armass.c @@ -5813,7 +5813,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) { } ao->o |= ((ret >> 16) & 0xff) << 8; ao->o |= ((ret >> 8) & 0xff) << 16; - ao->o |= ((ret) & 0xff) << 24; + ao->o |= ((ret)&0xff) << 24; } else { RZ_LOG_ERROR("assembler: arm: %s: instruction does not accept a register as argument\n", ops[i].name); return 0; @@ -5839,7 +5839,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) { dst /= 4; ao->o |= ((dst >> 16) & 0xff) << 8; ao->o |= ((dst >> 8) & 0xff) << 16; - ao->o |= ((dst) & 0xff) << 24; + ao->o |= ((dst)&0xff) << 24; return 4; } else { ao->o |= (getreg(ao->a[0]) << 24); @@ -5850,7 +5850,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) { o |= ((n >> 12) & 0xf) << 8; o |= ((n >> 8) & 0xf) << 20; o |= ((n >> 4) & 0xf) << 16; - o |= ((n) & 0xf) << 24; + o |= ((n)&0xf) << 24; ao->o |= o; } break; case TYPE_SWI: From 084ae01263bdf7b8243d2b3d7a3b717d1a34c0a3 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Mon, 23 Oct 2023 09:01:54 -0500 Subject: [PATCH 17/19] Add return to assert cases. --- librz/analysis/p/analysis_arm_cs.c | 1 + librz/asm/arch/arm/arm_it.c | 1 + librz/asm/p/asm_arm_cs.c | 1 + 3 files changed, 3 insertions(+) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index 838eb342076..0e2ce3a7edd 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -19,6 +19,7 @@ inline static const char *ARMCondCodeToString(arm_cc cc) { switch (cc) { default: assert(0 && "Unknown condition code"); + return ""; case ARM_CC_EQ: return "eq"; case ARM_CC_NE: diff --git a/librz/asm/arch/arm/arm_it.c b/librz/asm/arch/arm/arm_it.c index 126e71236d4..09b189fcd9f 100644 --- a/librz/asm/arch/arm/arm_it.c +++ b/librz/asm/arch/arm/arm_it.c @@ -34,6 +34,7 @@ inline static arm_cc ARMCC_getOppositeCondition(arm_cc cc) { default: // llvm_unreachable("Unknown condition code"); assert(0); + return ARM_CC_INVALID; case ARM_CC_EQ: return ARM_CC_NE; case ARM_CC_NE: diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index 3098314b421..fa1ac56864b 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -21,6 +21,7 @@ inline static const char *ARMCondCodeToString(arm_cc cc) { switch (cc) { default: assert(0 && "Unknown condition code"); + return ""; case ARM_CC_EQ: return "eq"; case ARM_CC_NE: From 07dfaa42dd71533caa33f9d43eefed560947e30b Mon Sep 17 00:00:00 2001 From: wargio Date: Wed, 25 Oct 2023 14:37:22 +0800 Subject: [PATCH 18/19] Update cs to 46154e8605aaefdcca5fecf4ea88b92db5a40ad3 --- subprojects/capstone-next.wrap | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subprojects/capstone-next.wrap b/subprojects/capstone-next.wrap index 820104cdfdf..d94540dae98 100644 --- a/subprojects/capstone-next.wrap +++ b/subprojects/capstone-next.wrap @@ -1,5 +1,5 @@ [wrap-git] url = https://github.com/capstone-engine/capstone.git -revision = 1fc1011d669c893ecd7cb107d3a8e4976ff10e19 +revision = 46154e8605aaefdcca5fecf4ea88b92db5a40ad3 directory = capstone-next patch_directory = capstone-next From 453344fdd2bfd486e2d3a2f6d7df44473588f86d Mon Sep 17 00:00:00 2001 From: wargio Date: Wed, 25 Oct 2023 14:37:25 +0800 Subject: [PATCH 19/19] Remove cs3 wrap file. --- subprojects/capstone-v3.wrap | 6 ------ 1 file changed, 6 deletions(-) delete mode 100644 subprojects/capstone-v3.wrap diff --git a/subprojects/capstone-v3.wrap b/subprojects/capstone-v3.wrap deleted file mode 100644 index e99a2565532..00000000000 --- a/subprojects/capstone-v3.wrap +++ /dev/null @@ -1,6 +0,0 @@ -[wrap-file] -source_url = https://github.com/capstone-engine/capstone/archive/3.0.5.tar.gz -source_filename = 3.0.5.tar.gz -source_hash = 913dd695e7c5a2b972a6f427cb31f2e93677ec1c38f39dda37d18a91c70b6df1 -patch_directory = capstone-3.0.5 -directory = capstone-3.0.5