From af63f9e60b2f92111e4c79452987886cc8762303 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 25 Aug 2023 17:40:38 -0500 Subject: [PATCH] Remove no longer existing alias and some name changes. --- librz/analysis/arch/arm/arm_esil64.c | 142 ++++++++-------- librz/analysis/arch/arm/arm_il64.c | 234 +-------------------------- librz/analysis/p/analysis_arm_cs.c | 109 ++++--------- librz/include/rz_analysis.h | 1 + 4 files changed, 112 insertions(+), 374 deletions(-) diff --git a/librz/analysis/arch/arm/arm_esil64.c b/librz/analysis/arch/arm/arm_esil64.c index 0b81fd6463d..f69e2d08495 100644 --- a/librz/analysis/arch/arm/arm_esil64.c +++ b/librz/analysis/arch/arm/arm_esil64.c @@ -363,10 +363,10 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a rz_strbuf_setf(&op->esil, "%s,%s,*,%s,-,%s,=", REG64(2), REG64(1), REG64(3), REG64(0)); break; - case AArch64_INS_MNEG: - rz_strbuf_setf(&op->esil, "%s,%s,*,0,-,%s,=", - REG64(2), REG64(1), REG64(0)); - break; + // case AArch64_INS_MNEG: + // rz_strbuf_setf(&op->esil, "%s,%s,*,0,-,%s,=", + // REG64(2), REG64(1), REG64(0)); + // break; case AArch64_INS_ADD: case AArch64_INS_ADC: // Add with carry. // case AArch64_INS_ADCS: // Add with carry. @@ -445,7 +445,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a case AArch64_INS_ROR: OPCALL(">>>"); break; - case AArch64_INS_NOP: + case AArch64_INS_HINT: rz_strbuf_setf(&op->esil, ","); break; case AArch64_INS_FDIV: @@ -733,9 +733,9 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a case AArch64_INS_FCMP: case AArch64_INS_CCMP: case AArch64_INS_CCMN: - case AArch64_INS_TST: // cmp w8, 0xd - case AArch64_INS_CMP: // cmp w8, 0xd - case AArch64_INS_CMN: // cmp w8, 0xd + // case AArch64_INS_TST: // cmp w8, 0xd + // case AArch64_INS_CMP: // cmp w8, 0xd + // case AArch64_INS_CMN: // cmp w8, 0xd { // update esil, cpu flags int bits = aarch64_reg_width(REGID64(0)); @@ -753,18 +753,18 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a rz_strbuf_appendf(&op->esil, "%s,}{,%s,},%s,=", REG64(1), REG64(2), REG64(0)); postfix = ""; break; - case AArch64_INS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0 - rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0)); - postfix = ""; - break; - case AArch64_INS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn - rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0)); - postfix = ""; - break; - case AArch64_INS_CSINC: // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1) - rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0)); - postfix = ""; - break; + // case AArch64_INS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0 + // rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0)); + // postfix = ""; + // break; + // case AArch64_INS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn + // rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0)); + // postfix = ""; + // break; + // case AArch64_INS_CSINC: // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1) + // rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0)); + // postfix = ""; + // break; case AArch64_INS_STXRB: case AArch64_INS_STXRH: case AArch64_INS_STXR: { @@ -1000,7 +1000,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a rz_strbuf_setf(&op->esil, "0xffffffff00000000,0x20,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x20,0xffffffff00000000,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,%2$s,=", REG64(1), REG64(0)); break; - case AArch64_INS_MVN: + // case AArch64_INS_MVN: case AArch64_INS_MOVN: if (ISREG64(1)) { rz_strbuf_setf(&op->esil, "%d,%s,-1,^,<<,%s,=", LSHIFT2_64(1), REG64(1), REG64(0)); @@ -1090,56 +1090,56 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a case AArch64_INS_ERET: rz_strbuf_setf(&op->esil, "lr,pc,="); break; - case AArch64_INS_BFI: // bfi w8, w8, 2, 1 - case AArch64_INS_BFXIL: { - if (OPCOUNT64() >= 3 && ISIMM64(3) && IMM64(3) > 0) { - ut64 mask = rz_num_bitmask((ut8)IMM64(3)); - ut64 shift = IMM64(2); - ut64 notmask = ~(mask << shift); - // notmask,dst,&,lsb,mask,src,&,<<,|,dst,= - rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,&,%" PFMT64u ",%" PFMT64u ",%s,&,<<,|,%s,=", - notmask, REG64(0), shift, mask, REG64(1), REG64(0)); - } - break; - } - case AArch64_INS_SBFIZ: - if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { - rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=", - IMM64(2), IMM64(3), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); - } - break; - case AArch64_INS_UBFIZ: - if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { - rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=", - IMM64(2), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); - } - break; - case AArch64_INS_SBFX: - if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { - rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=", - IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); - } - break; - case AArch64_INS_UBFX: - if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { - rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=", - IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); - } - break; - case AArch64_INS_NEG: -#if CS_API_MAJOR > 3 - case AArch64_INS_NEGS: -#endif - if (LSHIFT2_64(1)) { - SHIFTED_REG64_APPEND(&op->esil, 1); - } else { - rz_strbuf_appendf(&op->esil, "%s", REG64(1)); - } - rz_strbuf_appendf(&op->esil, ",0,-,%s,=", REG64(0)); - break; - case AArch64_INS_SVC: - rz_strbuf_setf(&op->esil, "%" PFMT64u ",$", IMM64(0)); - break; + // case AArch64_INS_BFI: // bfi w8, w8, 2, 1 + // case AArch64_INS_BFXIL: { + // if (OPCOUNT64() >= 3 && ISIMM64(3) && IMM64(3) > 0) { + // ut64 mask = rz_num_bitmask((ut8)IMM64(3)); + // ut64 shift = IMM64(2); + // ut64 notmask = ~(mask << shift); + // // notmask,dst,&,lsb,mask,src,&,<<,|,dst,= + // rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,&,%" PFMT64u ",%" PFMT64u ",%s,&,<<,|,%s,=", + // notmask, REG64(0), shift, mask, REG64(1), REG64(0)); + // } + // break; + // } +// case AArch64_INS_SBFIZ: +// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { +// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=", +// IMM64(2), IMM64(3), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); +// } +// break; +// case AArch64_INS_UBFIZ: +// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { +// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=", +// IMM64(2), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); +// } +// break; +// case AArch64_INS_SBFX: +// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { +// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=", +// IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); +// } +// break; +// case AArch64_INS_UBFX: +// if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { +// rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=", +// IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); +// } +// break; +// case AArch64_INS_NEG: +// #if CS_API_MAJOR > 3 +// case AArch64_INS_NEGS: +// #endif +// if (LSHIFT2_64(1)) { +// SHIFTED_REG64_APPEND(&op->esil, 1); +// } else { +// rz_strbuf_appendf(&op->esil, "%s", REG64(1)); +// } +// rz_strbuf_appendf(&op->esil, ",0,-,%s,=", REG64(0)); +// break; +// case AArch64_INS_SVC: +// rz_strbuf_setf(&op->esil, "%" PFMT64u ",$", IMM64(0)); +// break; } rz_strbuf_append(&op->esil, postfix); diff --git a/librz/analysis/arch/arm/arm_il64.c b/librz/analysis/arch/arm/arm_il64.c index 464d12a8934..c3240b8343e 100644 --- a/librz/analysis/arch/arm/arm_il64.c +++ b/librz/analysis/arch/arm/arm_il64.c @@ -650,10 +650,7 @@ static RzILOpEffect *bfm(cs_insn *insn) { } ut64 mask_base = rz_num_bitmask(IMM(3)); ut64 mask = mask_base << RZ_MIN(63, IMM(2)); - if (insn->id == AArch64_INS_BFI) { - return write_reg(REGID(0), LOGOR(LOGAND(a, UN(bits, ~mask)), SHIFTL0(LOGAND(b, UN(bits, mask_base)), UN(6, IMM(2))))); - } - // insn->id == AArch64_INS_BFXIL + // insn->id == AArch64_INS_BFM return write_reg(REGID(0), LOGOR(LOGAND(a, UN(bits, ~mask_base)), SHIFTR0(LOGAND(b, UN(bits, mask)), UN(6, IMM(2))))); } @@ -811,7 +808,7 @@ static RzILOpEffect *cmp(cs_insn *insn) { rz_il_op_pure_free(b); return NULL; } - bool is_neg = insn->id == AArch64_INS_CMN || insn->id == AArch64_INS_CCMN; + bool is_neg = insn->id == AArch64_INS_CCMN; RzILOpEffect *eff = SEQ6( SETL("a", a), SETL("b", b), @@ -872,14 +869,10 @@ static RzILOpEffect *csinc(cs_insn *insn) { break; case AArch64_INS_CSINV: invert_cond = true; - // fallthrough - case AArch64_INS_CINV: res = LOGNOT(src1); break; case AArch64_INS_CSNEG: invert_cond = true; - // fallthrough - case AArch64_INS_CNEG: res = NEG(src1); break; case AArch64_INS_CSINC: @@ -892,22 +885,6 @@ static RzILOpEffect *csinc(cs_insn *insn) { return write_reg(REGID(dst_idx), invert_cond ? ITE(c, src0, res) : ITE(c, res, src0)); } -/** - * Capstone: AArch64_INS_CSET, AArch64_INS_CSETM - * ARM: cset, csetm - */ -static RzILOpEffect *cset(cs_insn *insn) { - if (!ISREG(0) || !REGBITS(0)) { - return NULL; - } - RzILOpBool *c = cond(insn->detail->aarch64.cc); - if (!c) { - return NULL; - } - ut32 bits = REGBITS(0); - return write_reg(REGID(0), ITE(c, SN(bits, insn->id == AArch64_INS_CSETM ? -1 : 1), SN(bits, 0))); -} - /** * Capstone: AArch64_INS_CLS * ARM: cls @@ -1318,8 +1295,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDCLRAB: case AArch64_INS_LDCLRALB: case AArch64_INS_LDCLRLB: - case AArch64_INS_STCLRB: - case AArch64_INS_STCLRLB: op = OP_CLR; loadsz = 8; break; @@ -1327,8 +1302,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDEORAB: case AArch64_INS_LDEORALB: case AArch64_INS_LDEORLB: - case AArch64_INS_STEORB: - case AArch64_INS_STEORLB: op = OP_EOR; loadsz = 8; break; @@ -1336,8 +1309,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDSETAB: case AArch64_INS_LDSETALB: case AArch64_INS_LDSETLB: - case AArch64_INS_STSETB: - case AArch64_INS_STSETLB: op = OP_SET; loadsz = 8; break; @@ -1345,8 +1316,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDSMAXAB: case AArch64_INS_LDSMAXALB: case AArch64_INS_LDSMAXLB: - case AArch64_INS_STSMAXB: - case AArch64_INS_STSMAXLB: op = OP_SMAX; loadsz = 8; break; @@ -1354,8 +1323,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDSMINAB: case AArch64_INS_LDSMINALB: case AArch64_INS_LDSMINLB: - case AArch64_INS_STSMINB: - case AArch64_INS_STSMINLB: op = OP_SMIN; loadsz = 8; break; @@ -1363,8 +1330,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDUMAXAB: case AArch64_INS_LDUMAXALB: case AArch64_INS_LDUMAXLB: - case AArch64_INS_STUMAXB: - case AArch64_INS_STUMAXLB: op = OP_UMAX; loadsz = 8; break; @@ -1372,8 +1337,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDUMINAB: case AArch64_INS_LDUMINALB: case AArch64_INS_LDUMINLB: - case AArch64_INS_STUMINB: - case AArch64_INS_STUMINLB: op = OP_UMIN; loadsz = 8; break; @@ -1381,8 +1344,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDADDAB: case AArch64_INS_LDADDALB: case AArch64_INS_LDADDLB: - case AArch64_INS_STADDB: - case AArch64_INS_STADDLB: loadsz = 8; break; @@ -1390,8 +1351,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDCLRAH: case AArch64_INS_LDCLRALH: case AArch64_INS_LDCLRLH: - case AArch64_INS_STCLRH: - case AArch64_INS_STCLRLH: op = OP_CLR; loadsz = 16; break; @@ -1399,8 +1358,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDEORAH: case AArch64_INS_LDEORALH: case AArch64_INS_LDEORLH: - case AArch64_INS_STEORH: - case AArch64_INS_STEORLH: op = OP_EOR; loadsz = 16; break; @@ -1408,8 +1365,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDSETAH: case AArch64_INS_LDSETALH: case AArch64_INS_LDSETLH: - case AArch64_INS_STSETH: - case AArch64_INS_STSETLH: op = OP_SET; loadsz = 16; break; @@ -1417,8 +1372,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDSMAXAH: case AArch64_INS_LDSMAXALH: case AArch64_INS_LDSMAXLH: - case AArch64_INS_STSMAXH: - case AArch64_INS_STSMAXLH: op = OP_SMAX; loadsz = 16; break; @@ -1426,8 +1379,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDSMINAH: case AArch64_INS_LDSMINALH: case AArch64_INS_LDSMINLH: - case AArch64_INS_STSMINH: - case AArch64_INS_STSMINLH: op = OP_SMIN; loadsz = 16; break; @@ -1435,8 +1386,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDUMAXAH: case AArch64_INS_LDUMAXALH: case AArch64_INS_LDUMAXLH: - case AArch64_INS_STUMAXH: - case AArch64_INS_STUMAXLH: op = OP_UMAX; loadsz = 16; break; @@ -1444,8 +1393,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDUMINAH: case AArch64_INS_LDUMINALH: case AArch64_INS_LDUMINLH: - case AArch64_INS_STUMINH: - case AArch64_INS_STUMINLH: op = OP_UMIN; loadsz = 16; break; @@ -1453,8 +1400,6 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDADDAH: case AArch64_INS_LDADDALH: case AArch64_INS_LDADDLH: - case AArch64_INS_STADDH: - case AArch64_INS_STADDLH: loadsz = 16; break; @@ -1462,56 +1407,42 @@ static RzILOpEffect *ldadd(cs_insn *insn) { case AArch64_INS_LDCLRA: case AArch64_INS_LDCLRAL: case AArch64_INS_LDCLRL: - case AArch64_INS_STCLR: - case AArch64_INS_STCLRL: op = OP_CLR; goto size_from_reg; case AArch64_INS_LDEOR: case AArch64_INS_LDEORA: case AArch64_INS_LDEORAL: case AArch64_INS_LDEORL: - case AArch64_INS_STEOR: - case AArch64_INS_STEORL: op = OP_EOR; goto size_from_reg; case AArch64_INS_LDSET: case AArch64_INS_LDSETA: case AArch64_INS_LDSETAL: case AArch64_INS_LDSETL: - case AArch64_INS_STSET: - case AArch64_INS_STSETL: op = OP_SET; goto size_from_reg; case AArch64_INS_LDSMAX: case AArch64_INS_LDSMAXA: case AArch64_INS_LDSMAXAL: case AArch64_INS_LDSMAXL: - case AArch64_INS_STSMAX: - case AArch64_INS_STSMAXL: op = OP_SMAX; goto size_from_reg; case AArch64_INS_LDSMIN: case AArch64_INS_LDSMINA: case AArch64_INS_LDSMINAL: case AArch64_INS_LDSMINL: - case AArch64_INS_STSMIN: - case AArch64_INS_STSMINL: op = OP_SMIN; goto size_from_reg; case AArch64_INS_LDUMAX: case AArch64_INS_LDUMAXA: case AArch64_INS_LDUMAXAL: case AArch64_INS_LDUMAXL: - case AArch64_INS_STUMAX: - case AArch64_INS_STUMAXL: op = OP_UMAX; goto size_from_reg; case AArch64_INS_LDUMIN: case AArch64_INS_LDUMINA: case AArch64_INS_LDUMINAL: case AArch64_INS_LDUMINL: - case AArch64_INS_STUMIN: - case AArch64_INS_STUMINL: op = OP_UMIN; // fallthrough size_from_reg: @@ -1631,9 +1562,6 @@ static RzILOpEffect *mul(cs_insn *insn) { return NULL; } RzILOpBitVector *res = MUL(ma, mb); - if (insn->id == AArch64_INS_MNEG) { - res = NEG(res); - } return write_reg(REGID(0), res); } @@ -1707,15 +1635,9 @@ static RzILOpEffect *movn(cs_insn *insn) { */ static RzILOpEffect *msr(cs_insn *insn) { cs_aarch64_op *op = &insn->detail->aarch64.operands[0]; -#if CS_API_MAJOR > 4 - if (op->type != AArch64_OP_SYS || (ut64)op->sys != (ut64)ARM64_SYSREG_NZCV) { - return NULL; - } -#else - if (op->type != AArch64_OP_REG_MSR || op->reg != 0xda10) { + if (op->type != AArch64_OP_SYSREG || op->sysop.sub_type == AArch64_OP_REG_MRS || op->sysop.reg.sysreg != AArch64_SYSREG_NZCV) { return NULL; } -#endif ut32 bits = 0; RzILOpBitVector *val = ARG(1, &bits); if (!val) { @@ -1763,36 +1685,6 @@ static RzILOpEffect *rmif(cs_insn *insn) { } #endif -/** - * Capstone: AArch64_INS_SBFX, AArch64_INS_SBFIZ, AArch64_INS_UBFX, AArch64_INS_UBFIZ - * ARM: sbfx, sbfiz, ubfx, ubfiz - */ -static RzILOpEffect *sbfx(cs_insn *insn) { - if (!ISREG(0) || !ISIMM(2) || !ISIMM(3)) { - return NULL; - } - ut32 bits = REGBITS(0); - if (!bits) { - return NULL; - } - RzILOpBitVector *src = ARG(1, &bits); - if (!src) { - return NULL; - } - ut64 lsb = IMM(2); - ut64 width = IMM(3); - RzILOpBitVector *res; - if (insn->id == AArch64_INS_SBFIZ || insn->id == AArch64_INS_UBFIZ) { - res = SHIFTL0(UNSIGNED(width + lsb, src), UN(6, lsb)); - } else { - // AArch64_INS_SBFX, AArch64_INS_UBFX - res = UNSIGNED(width, SHIFTR0(src, UN(6, lsb))); - } - bool is_signed = insn->id == AArch64_INS_SBFX || insn->id == AArch64_INS_SBFIZ; - res = LET("res", res, is_signed ? SIGNED(bits, VARLP("res")) : UNSIGNED(bits, VARLP("res"))); - return write_reg(REGID(0), res); -} - /** * Capstone: AArch64_INS_MRS * ARM: mrs @@ -1802,15 +1694,9 @@ static RzILOpEffect *mrs(cs_insn *insn) { return NULL; } cs_aarch64_op *op = &insn->detail->aarch64.operands[1]; -#if CS_API_MAJOR > 4 - if (op->type != AArch64_OP_SYS || (ut64)op->sys != (ut64)ARM64_SYSREG_NZCV) { - return NULL; - } -#else - if (op->type != AArch64_OP_REG_MRS || op->reg != 0xda10) { + if (op->type != AArch64_OP_SYSREG || op->sysop.sub_type == AArch64_OP_REG_MRS || op->reg != 0xda10) { return NULL; } -#endif ut32 bits = REGBITS(0); if (!bits) { return NULL; @@ -1838,17 +1724,8 @@ static RzILOpEffect *mvn(cs_insn *insn) { RzILOpBitVector *res; switch (insn->id) { case AArch64_INS_NEG: -#if CS_API_MAJOR > 3 - case AArch64_INS_NEGS: -#endif res = NEG(val); break; - case AArch64_INS_NGC: -#if CS_API_MAJOR > 3 - case AArch64_INS_NGCS: -#endif - res = NEG(ADD(val, ITE(VARG("cf"), UN(bits, 0), UN(bits, 1)))); - break; default: // AArch64_INS_MVN res = LOGNOT(val); break; @@ -1861,7 +1738,7 @@ static RzILOpEffect *mvn(cs_insn *insn) { return SEQ5( SETL("b", DUP(val)), set, - SETG("cf", sub_carry(UN(bits, 0), VARL("b"), insn->id == AArch64_INS_NGC, bits)), + SETG("cf", sub_carry(UN(bits, 0), VARL("b"), false, bits)), SETG("vf", sub_overflow(UN(bits, 0), VARL("b"), REG(0))), update_flags_zn(REG(0))); } @@ -2077,11 +1954,8 @@ static RzILOpEffect *smull(cs_insn *insn) { rz_il_op_pure_free(y); return NULL; } - bool is_signed = insn->id == AArch64_INS_SMULL || insn->id == AArch64_INS_SMNEGL; + bool is_signed = insn->id == AArch64_INS_SMULL; RzILOpBitVector *res = MUL(is_signed ? SIGNED(64, x) : UNSIGNED(64, x), is_signed ? SIGNED(64, y) : UNSIGNED(64, y)); - if (insn->id == AArch64_INS_SMNEGL || insn->id == AArch64_INS_UMNEGL) { - res = NEG(res); - } return write_reg(REGID(0), res); } @@ -2222,22 +2096,6 @@ static RzILOpEffect *tbz(cs_insn *insn) { : BRANCH(c, NULL, JMP(tgt)); } -/** - * Capstone: AArch64_INS_TST - * ARM: tst - */ -static RzILOpEffect *tst(cs_insn *insn) { - ut32 bits = 0; - RzILOpBitVector *a = ARG(0, &bits); - RzILOpBitVector *b = ARG(1, &bits); - if (!a || !b) { - rz_il_op_pure_free(a); - rz_il_op_pure_free(b); - return NULL; - } - return update_flags_zn00(LOGAND(a, b)); -} - /** * Lift an AArch64 instruction to RzIL * @@ -2315,15 +2173,9 @@ static RzILOpEffect *tst(cs_insn *insn) { */ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { switch (insn->id) { - case AArch64_INS_NOP: case AArch64_INS_HINT: case AArch64_INS_PRFM: case AArch64_INS_PRFUM: - case AArch64_INS_SEV: - case AArch64_INS_SEVL: - case AArch64_INS_WFE: - case AArch64_INS_WFI: - case AArch64_INS_YIELD: return NOP(); case AArch64_INS_ADD: case AArch64_INS_ADC: @@ -2375,8 +2227,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { #endif return bl(insn); case AArch64_INS_BFM: - case AArch64_INS_BFI: - case AArch64_INS_BFXIL: return bfm(insn); case AArch64_INS_BIC: #if CS_API_MAJOR > 4 @@ -2406,8 +2256,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_CBZ: case AArch64_INS_CBNZ: return cbz(insn); - case AArch64_INS_CMP: - case AArch64_INS_CMN: case AArch64_INS_CCMP: case AArch64_INS_CCMN: return cmp(insn); @@ -2415,17 +2263,11 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_CFINV: return SETG("cf", INV(VARG("cf"))); #endif - case AArch64_INS_CINC: case AArch64_INS_CSINC: - case AArch64_INS_CINV: case AArch64_INS_CSINV: - case AArch64_INS_CNEG: case AArch64_INS_CSNEG: case AArch64_INS_CSEL: return csinc(insn); - case AArch64_INS_CSET: - case AArch64_INS_CSETM: - return cset(insn); case AArch64_INS_CLS: return cls(insn); case AArch64_INS_CLZ: @@ -2498,12 +2340,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDADDAH: case AArch64_INS_LDADDALH: case AArch64_INS_LDADDLH: - case AArch64_INS_STADD: - case AArch64_INS_STADDL: - case AArch64_INS_STADDB: - case AArch64_INS_STADDLB: - case AArch64_INS_STADDH: - case AArch64_INS_STADDLH: case AArch64_INS_LDCLRB: case AArch64_INS_LDCLRAB: case AArch64_INS_LDCLRALB: @@ -2516,12 +2352,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDCLRA: case AArch64_INS_LDCLRAL: case AArch64_INS_LDCLRL: - case AArch64_INS_STCLR: - case AArch64_INS_STCLRL: - case AArch64_INS_STCLRB: - case AArch64_INS_STCLRLB: - case AArch64_INS_STCLRH: - case AArch64_INS_STCLRLH: case AArch64_INS_LDEORB: case AArch64_INS_LDEORAB: case AArch64_INS_LDEORALB: @@ -2534,12 +2364,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDEORA: case AArch64_INS_LDEORAL: case AArch64_INS_LDEORL: - case AArch64_INS_STEOR: - case AArch64_INS_STEORL: - case AArch64_INS_STEORB: - case AArch64_INS_STEORLB: - case AArch64_INS_STEORH: - case AArch64_INS_STEORLH: case AArch64_INS_LDSETB: case AArch64_INS_LDSETAB: case AArch64_INS_LDSETALB: @@ -2552,12 +2376,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDSETA: case AArch64_INS_LDSETAL: case AArch64_INS_LDSETL: - case AArch64_INS_STSET: - case AArch64_INS_STSETL: - case AArch64_INS_STSETB: - case AArch64_INS_STSETLB: - case AArch64_INS_STSETH: - case AArch64_INS_STSETLH: case AArch64_INS_LDSMAXB: case AArch64_INS_LDSMAXAB: case AArch64_INS_LDSMAXALB: @@ -2570,12 +2388,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDSMAXA: case AArch64_INS_LDSMAXAL: case AArch64_INS_LDSMAXL: - case AArch64_INS_STSMAX: - case AArch64_INS_STSMAXL: - case AArch64_INS_STSMAXB: - case AArch64_INS_STSMAXLB: - case AArch64_INS_STSMAXH: - case AArch64_INS_STSMAXLH: case AArch64_INS_LDSMINB: case AArch64_INS_LDSMINAB: case AArch64_INS_LDSMINALB: @@ -2588,12 +2400,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDSMINA: case AArch64_INS_LDSMINAL: case AArch64_INS_LDSMINL: - case AArch64_INS_STSMIN: - case AArch64_INS_STSMINL: - case AArch64_INS_STSMINB: - case AArch64_INS_STSMINLB: - case AArch64_INS_STSMINH: - case AArch64_INS_STSMINLH: case AArch64_INS_LDUMAXB: case AArch64_INS_LDUMAXAB: case AArch64_INS_LDUMAXALB: @@ -2606,12 +2412,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDUMAXA: case AArch64_INS_LDUMAXAL: case AArch64_INS_LDUMAXL: - case AArch64_INS_STUMAX: - case AArch64_INS_STUMAXL: - case AArch64_INS_STUMAXB: - case AArch64_INS_STUMAXLB: - case AArch64_INS_STUMAXH: - case AArch64_INS_STUMAXLH: case AArch64_INS_LDUMINB: case AArch64_INS_LDUMINAB: case AArch64_INS_LDUMINALB: @@ -2624,19 +2424,12 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_LDUMINA: case AArch64_INS_LDUMINAL: case AArch64_INS_LDUMINL: - case AArch64_INS_STUMIN: - case AArch64_INS_STUMINL: - case AArch64_INS_STUMINB: - case AArch64_INS_STUMINLB: - case AArch64_INS_STUMINH: - case AArch64_INS_STUMINLH: return ldadd(insn); #endif case AArch64_INS_MADD: case AArch64_INS_MSUB: return madd(insn); case AArch64_INS_MUL: - case AArch64_INS_MNEG: return mul(insn); case AArch64_INS_MOV: case AArch64_INS_MOVZ: @@ -2649,13 +2442,7 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { return msr(insn); case AArch64_INS_MRS: return mrs(insn); - case AArch64_INS_MVN: case AArch64_INS_NEG: - case AArch64_INS_NGC: -#if CS_API_MAJOR > 3 - case AArch64_INS_NEGS: - case AArch64_INS_NGCS: -#endif return mvn(insn); case AArch64_INS_RBIT: return rbit(insn); @@ -2667,11 +2454,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_RMIF: return rmif(insn); #endif - case AArch64_INS_SBFIZ: - case AArch64_INS_SBFX: - case AArch64_INS_UBFIZ: - case AArch64_INS_UBFX: - return sbfx(insn); case AArch64_INS_SDIV: return sdiv(insn); #if CS_API_MAJOR > 4 @@ -2685,9 +2467,7 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_UMSUBL: return smaddl(insn); case AArch64_INS_SMULL: - case AArch64_INS_SMNEGL: case AArch64_INS_UMULL: - case AArch64_INS_UMNEGL: return smull(insn); case AArch64_INS_SMULH: case AArch64_INS_UMULH: @@ -2747,8 +2527,6 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { case AArch64_INS_TBNZ: case AArch64_INS_TBZ: return tbz(insn); - case AArch64_INS_TST: - return tst(insn); case AArch64_INS_UDIV: return udiv(insn); default: diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index a9471a2a6a7..f7609f11138 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -13,6 +13,7 @@ #include "../arch/arm/arm_accessors32.h" #include "../arch/arm/arm_accessors64.h" #include "../../asm/arch/arm/arm_it.h" +#include "aarch64.h" typedef struct arm_cs_context_t { RzArmITContext it; @@ -326,58 +327,39 @@ static const char *extender_name(aarch64_extender extender) { static const char *vas_name(AArch64Layout_VectorLayout vas) { switch (vas) { - case ARM64_VAS_8B: + case AArch64Layout_VL_B: + return "b"; + case AArch64Layout_VL_H: + return "h"; + case AArch64Layout_VL_S: + return "s"; + case AArch64Layout_VL_D: + return "d"; + case AArch64Layout_VL_Q: + return "q"; + case AArch64Layout_VL_8B: return "8b"; - case ARM64_VAS_16B: + case AArch64Layout_VL_16B: return "16b"; - case ARM64_VAS_4H: + case AArch64Layout_VL_4H: return "4h"; - case ARM64_VAS_8H: + case AArch64Layout_VL_8H: return "8h"; - case ARM64_VAS_2S: + case AArch64Layout_VL_2S: return "2s"; - case ARM64_VAS_4S: + case AArch64Layout_VL_4S: return "4s"; - case ARM64_VAS_2D: + case AArch64Layout_VL_2D: return "2d"; - case ARM64_VAS_1D: + case AArch64Layout_VL_1D: return "1d"; - case ARM64_VAS_1Q: + case AArch64Layout_VL_1Q: return "1q"; -#if CS_API_MAJOR > 4 - case ARM64_VAS_1B: - return "8b"; - case ARM64_VAS_4B: - return "8b"; - case ARM64_VAS_2H: - return "2h"; - case ARM64_VAS_1H: - return "1h"; - case ARM64_VAS_1S: - return "1s"; -#endif default: return ""; } } -#if CS_API_MAJOR == 4 -static const char *vess_name(arm64_vess vess) { - switch (vess) { - case ARM64_VESS_B: - return "b"; - case ARM64_VESS_H: - return "h"; - case ARM64_VESS_S: - return "s"; - case ARM64_VESS_D: - return "d"; - default: - return ""; - } -} -#endif - static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { int i; PJ *pj = pj_new(); @@ -487,7 +469,7 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { if (op->vector_index != -1) { pj_ki(pj, "vector_index", op->vector_index); } - if (op->vas != ARM64_VAS_INVALID) { + if (op->vas != AArch64Layout_Invalid) { pj_ks(pj, "vas", vas_name(op->vas)); } #if CS_API_MAJOR == 4 @@ -501,10 +483,10 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { if (x->update_flags) { pj_kb(pj, "update_flags", true); } - if (x->writeback) { + if (insn->detail->writeback) { pj_kb(pj, "writeback", true); } - if (x->cc != AArch64CC_INVALID && x->cc != AArch64CC_AL && x->cc != AArch64CC_NV) { + if (x->cc != AArch64CC_AL && x->cc != AArch64CC_NV) { pj_ks(pj, "cc", cc_name64(x->cc)); } pj_end(pj); @@ -567,17 +549,17 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { ut64 addr = op->addr; /* grab family */ - if (cs_insn_group(handle, insn, ARM64_GRP_CRYPTO)) { + if (cs_insn_group(handle, insn, AArch64_FEATURE_HasAES)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; - } else if (cs_insn_group(handle, insn, ARM64_GRP_CRC)) { + } else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasCRC)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; #if CS_API_MAJOR >= 4 - } else if (cs_insn_group(handle, insn, ARM64_GRP_PRIVILEGE)) { + } else if (cs_insn_group(handle, insn, AArch64_GRP_PRIVILEGE)) { op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; #endif - } else if (cs_insn_group(handle, insn, ARM64_GRP_NEON)) { + } else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasNEON)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; - } else if (cs_insn_group(handle, insn, ARM64_GRP_FPARMV8)) { + } else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasFPARMv8)) { op->family = RZ_ANALYSIS_OP_FAMILY_FPU; } else { op->family = RZ_ANALYSIS_OP_FAMILY_CPU; @@ -608,13 +590,7 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { case AArch64_INS_PACDZB: case AArch64_INS_PACGA: case AArch64_INS_PACIA: - case AArch64_INS_PACIA1716: - case AArch64_INS_PACIASP: - case AArch64_INS_PACIAZ: case AArch64_INS_PACIB: - case AArch64_INS_PACIB1716: - case AArch64_INS_PACIBSP: - case AArch64_INS_PACIBZ: case AArch64_INS_PACIZA: case AArch64_INS_PACIZB: case AArch64_INS_AUTDA: @@ -622,18 +598,11 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { case AArch64_INS_AUTDZA: case AArch64_INS_AUTDZB: case AArch64_INS_AUTIA: - case AArch64_INS_AUTIA1716: - case AArch64_INS_AUTIASP: - case AArch64_INS_AUTIAZ: case AArch64_INS_AUTIB: - case AArch64_INS_AUTIB1716: - case AArch64_INS_AUTIBSP: - case AArch64_INS_AUTIBZ: case AArch64_INS_AUTIZA: case AArch64_INS_AUTIZB: case AArch64_INS_XPACD: case AArch64_INS_XPACI: - case AArch64_INS_XPACLRI: op->type = RZ_ANALYSIS_OP_TYPE_CMP; op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY; break; @@ -647,8 +616,12 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->type = RZ_ANALYSIS_OP_TYPE_LEA; op->ptr = IMM64(1); break; - case AArch64_INS_NOP: - op->type = RZ_ANALYSIS_OP_TYPE_NOP; + case AArch64_INS_HINT: + if (insn->alias_id == AArch64_INS_ALIAS_NOP) { + op->type = RZ_ANALYSIS_OP_TYPE_NOP; + } else { + op->type = RZ_ANALYSIS_OP_TYPE_HINT; + } op->cycles = 1; break; case AArch64_INS_SUB: @@ -709,8 +682,6 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { break; case AArch64_INS_CSEL: case AArch64_INS_FCSEL: - case AArch64_INS_CSET: - case AArch64_INS_CINC: op->type = RZ_ANALYSIS_OP_TYPE_CMOV; break; case AArch64_INS_MOV: @@ -729,14 +700,8 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { case AArch64_INS_SMOV: case AArch64_INS_UMOV: case AArch64_INS_FMOV: - case AArch64_INS_SBFX: - case AArch64_INS_UBFX: case AArch64_INS_UBFM: - case AArch64_INS_SBFIZ: - case AArch64_INS_UBFIZ: case AArch64_INS_BIC: - case AArch64_INS_BFI: - case AArch64_INS_BFXIL: op->type = RZ_ANALYSIS_OP_TYPE_MOV; break; case AArch64_INS_MRS: @@ -807,17 +772,11 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->type = RZ_ANALYSIS_OP_TYPE_SAR; break; case AArch64_INS_NEG: -#if CS_API_MAJOR > 3 - case AArch64_INS_NEGS: -#endif op->type = RZ_ANALYSIS_OP_TYPE_NOT; break; case AArch64_INS_FCMP: case AArch64_INS_CCMP: case AArch64_INS_CCMN: - case AArch64_INS_CMP: - case AArch64_INS_CMN: - case AArch64_INS_TST: op->type = RZ_ANALYSIS_OP_TYPE_CMP; break; case AArch64_INS_ROR: diff --git a/librz/include/rz_analysis.h b/librz/include/rz_analysis.h index 91ccf9e67c8..2cb49f62995 100644 --- a/librz/include/rz_analysis.h +++ b/librz/include/rz_analysis.h @@ -337,6 +337,7 @@ typedef enum { RZ_ANALYSIS_OP_TYPE_CPL = 45, /* complement */ RZ_ANALYSIS_OP_TYPE_CRYPTO = 46, RZ_ANALYSIS_OP_TYPE_SYNC = 47, + RZ_ANALYSIS_OP_TYPE_HINT = 48, ///< A hint instruction. Does nothing. // RZ_ANALYSIS_OP_TYPE_DEBUG = 43, // monitor/trace/breakpoint #if 0 RZ_ANALYSIS_OP_TYPE_PRIV = 40, /* privileged instruction */