From 6df64dbbe868b541dbef7888e241a09d977ec264 Mon Sep 17 00:00:00 2001 From: Bastian Engel Date: Fri, 13 Oct 2023 18:15:03 +0200 Subject: [PATCH] Renesas RL78 disassembler plugin (#3649) --- librz/analysis/meson.build | 8 +- librz/analysis/p/analysis_rl78.c | 275 +++ librz/asm/arch/rl78/rl78.c | 271 +++ librz/asm/arch/rl78/rl78.h | 15 + librz/asm/arch/rl78/rl78_instr.c | 123 ++ librz/asm/arch/rl78/rl78_instr.h | 116 ++ librz/asm/arch/rl78/rl78_maps.c | 2661 ++++++++++++++++++++++++++++ librz/asm/arch/rl78/rl78_maps.h | 11 + librz/asm/arch/rl78/rl78_operand.c | 136 ++ librz/asm/arch/rl78/rl78_operand.h | 107 ++ librz/asm/d/rl78.sdb.txt | 76 + librz/asm/meson.build | 6 + librz/asm/p/asm_rl78.c | 54 + librz/include/rz_analysis.h | 1 + librz/include/rz_asm.h | 1 + test/db/analysis/rl78 | 205 +++ test/db/asm/rl78 | 1331 ++++++++++++++ test/db/cmd/cmd_list | 4 +- 18 files changed, 5399 insertions(+), 2 deletions(-) create mode 100644 librz/analysis/p/analysis_rl78.c create mode 100644 librz/asm/arch/rl78/rl78.c create mode 100644 librz/asm/arch/rl78/rl78.h create mode 100644 librz/asm/arch/rl78/rl78_instr.c create mode 100644 librz/asm/arch/rl78/rl78_instr.h create mode 100644 librz/asm/arch/rl78/rl78_maps.c create mode 100644 librz/asm/arch/rl78/rl78_maps.h create mode 100644 librz/asm/arch/rl78/rl78_operand.c create mode 100644 librz/asm/arch/rl78/rl78_operand.h create mode 100644 librz/asm/d/rl78.sdb.txt create mode 100644 librz/asm/p/asm_rl78.c create mode 100644 test/db/analysis/rl78 create mode 100644 test/db/asm/rl78 diff --git a/librz/analysis/meson.build b/librz/analysis/meson.build index 45ed273ae89..2c01de8e2f6 100644 --- a/librz/analysis/meson.build +++ b/librz/analysis/meson.build @@ -29,6 +29,7 @@ analysis_plugins_list = [ 'ppc_cs', 'propeller', 'pyc', + 'rl78', 'rsp', 'snes', 'sparc_cs', @@ -139,6 +140,7 @@ rz_analysis_sources = [ 'p/analysis_ppc_cs.c', 'p/analysis_propeller.c', 'p/analysis_pyc.c', + 'p/analysis_rl78.c', 'p/analysis_rsp.c', 'p/analysis_snes.c', 'p/analysis_sparc_cs.c', @@ -230,7 +232,11 @@ rz_analysis_sources = [ '../asm/arch/luac/v54/analysis_54.c', '../asm/arch/luac/v54/opcode_54.c', '../asm/arch/luac/v53/analysis_53.c', - '../asm/arch/luac/v53/opcode_53.c' + '../asm/arch/luac/v53/opcode_53.c', + '../asm/arch/rl78/rl78_instr.c', + '../asm/arch/rl78/rl78_maps.c', + '../asm/arch/rl78/rl78_operand.c', + '../asm/arch/rl78/rl78.c' ] if capstone_dep.version() == 'next' or capstone_dep.version().split('.')[0].to_int() > 4 diff --git a/librz/analysis/p/analysis_rl78.c b/librz/analysis/p/analysis_rl78.c new file mode 100644 index 00000000000..760c15a177a --- /dev/null +++ b/librz/analysis/p/analysis_rl78.c @@ -0,0 +1,275 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include +#include +#include +#include "../../asm/arch/rl78/rl78_instr.h" +#include "../../asm/arch/rl78/rl78.h" + +static int rl78_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask); +static void populate_jump_fields(const RL78Instr *instr, size_t instr_size, ut64 addr, RzAnalysisOp *op); +static char *get_reg_profile(RzAnalysis *analysis); + +static int rl78_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask) { + op->addr = addr; + op->type = RZ_ANALYSIS_OP_TYPE_ILL; + + RL78Instr instr = { 0 }; + size_t bytes_read = 0; + if (!rl78_dis(&instr, &bytes_read, buf, len)) { + op->size = bytes_read; + return bytes_read; + } else { + op->type = RZ_ANALYSIS_OP_TYPE_UNK; + } + + op->size = bytes_read; + op->addr = addr; + switch (instr.operation) { + case RL78_OPERATION_ADD: + case RL78_OPERATION_ADDC: + case RL78_OPERATION_ADDW: + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + break; + case RL78_OPERATION_AND: + case RL78_OPERATION_AND1: + op->type = RZ_ANALYSIS_OP_TYPE_AND; + break; + case RL78_OPERATION_BC: + case RL78_OPERATION_BF: + case RL78_OPERATION_BH: + case RL78_OPERATION_BNC: + case RL78_OPERATION_BNH: + case RL78_OPERATION_BNZ: + case RL78_OPERATION_BT: + case RL78_OPERATION_BTCLR: + case RL78_OPERATION_BZ: + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + populate_jump_fields(&instr, bytes_read, addr, op); + break; + case RL78_OPERATION_BR: + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + populate_jump_fields(&instr, bytes_read, addr, op); + break; + // conditional skip instructions + case RL78_OPERATION_SKC: + case RL78_OPERATION_SKH: + case RL78_OPERATION_SKNC: + case RL78_OPERATION_SKNH: + case RL78_OPERATION_SKNZ: + case RL78_OPERATION_SKZ: + // TODO set op->jump to instruction after next (i.e. skip) + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + break; + case RL78_OPERATION_BRK: + op->type = RZ_ANALYSIS_OP_TYPE_SWI; + break; + case RL78_OPERATION_CALL: + case RL78_OPERATION_CALLT: + op->type = RZ_ANALYSIS_OP_TYPE_CALL; + populate_jump_fields(&instr, bytes_read, addr, op); + break; + case RL78_OPERATION_CLRB: + case RL78_OPERATION_CLRW: + case RL78_OPERATION_CLR1: + // TODO (byte/word/bitclear) + break; + case RL78_OPERATION_CMP: + case RL78_OPERATION_CMPS: + case RL78_OPERATION_CMPW: + case RL78_OPERATION_CMP0: + op->type = RZ_ANALYSIS_OP_TYPE_CMP; + break; + case RL78_OPERATION_DEC: + case RL78_OPERATION_DECW: + case RL78_OPERATION_SUB: + case RL78_OPERATION_SUBC: + case RL78_OPERATION_SUBW: + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + break; + case RL78_OPERATION_EI: + case RL78_OPERATION_DI: + // TODO (interrupt enable/disable) + break; + case RL78_OPERATION_DIVHU: + case RL78_OPERATION_DIVWU: + op->type = RZ_ANALYSIS_OP_TYPE_DIV; + break; + case RL78_OPERATION_HALT: + // TODO (halt) + break; + case RL78_OPERATION_INC: + case RL78_OPERATION_INCW: + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + break; + case RL78_OPERATION_MULH: + case RL78_OPERATION_MULHU: + case RL78_OPERATION_MULU: + // multiply-and-accumulate + case RL78_OPERATION_MACH: + case RL78_OPERATION_MACHU: + op->type = RZ_ANALYSIS_OP_TYPE_MUL; + break; + case RL78_OPERATION_MOV: + case RL78_OPERATION_MOVS: + case RL78_OPERATION_MOVW: + case RL78_OPERATION_MOV1: + op->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; + case RL78_OPERATION_NOP: + op->type = RZ_ANALYSIS_OP_TYPE_NOP; + break; + case RL78_OPERATION_NOT1: + op->type = RZ_ANALYSIS_OP_TYPE_NOT; + break; + case RL78_OPERATION_ONEB: + case RL78_OPERATION_ONEW: + // TODO (byte/word set to 1) + break; + case RL78_OPERATION_OR: + case RL78_OPERATION_OR1: + op->type = RZ_ANALYSIS_OP_TYPE_OR; + break; + case RL78_OPERATION_POP: + op->type = RZ_ANALYSIS_OP_TYPE_POP; + break; + case RL78_OPERATION_PUSH: + op->type = RZ_ANALYSIS_OP_TYPE_PUSH; + break; + case RL78_OPERATION_RET: + op->type = RZ_ANALYSIS_OP_TYPE_RET; + break; + case RL78_OPERATION_RETB: + case RL78_OPERATION_RETI: + // TODO (return from software/hardware vectored interrupt) + break; + case RL78_OPERATION_ROL: + case RL78_OPERATION_ROLC: + case RL78_OPERATION_ROLWC: + op->type = RZ_ANALYSIS_OP_TYPE_ROL; + break; + case RL78_OPERATION_ROR: + case RL78_OPERATION_RORC: + op->type = RZ_ANALYSIS_OP_TYPE_ROR; + break; + case RL78_OPERATION_SAR: + case RL78_OPERATION_SARW: + op->type = RZ_ANALYSIS_OP_TYPE_SHR; + break; + case RL78_OPERATION_SEL: + case RL78_OPERATION_SET1: + case RL78_OPERATION_SHL: + case RL78_OPERATION_SHLW: + case RL78_OPERATION_SHR: + case RL78_OPERATION_SHRW: + op->type = RZ_ANALYSIS_OP_TYPE_SHL; + break; + case RL78_OPERATION_STOP: + // TODO (stop mode set) + break; + case RL78_OPERATION_XCH: + case RL78_OPERATION_XCHW: + op->type = RZ_ANALYSIS_OP_TYPE_XCHG; + break; + case RL78_OPERATION_XOR: + case RL78_OPERATION_XOR1: + op->type = RZ_ANALYSIS_OP_TYPE_XOR; + break; + default: + rz_warn_if_reached(); + break; + } + + return op->size; +} + +static void populate_jump_fields(const RL78Instr *instr, size_t instr_size, ut64 addr, RzAnalysisOp *op) { + const RL78Operand *target = &instr->op0; + if (instr->operation == RL78_OPERATION_BT || + instr->operation == RL78_OPERATION_BF || + instr->operation == RL78_OPERATION_BTCLR) { + target = &instr->op1; + } + + switch (target->type) { + case RL78_OP_TYPE_ABSOLUTE_ADDR_20: + case RL78_OP_TYPE_ABSOLUTE_ADDR_16: + op->jump = target->v0; + break; + case RL78_OP_TYPE_RELATIVE_ADDR_16: + case RL78_OP_TYPE_RELATIVE_ADDR_8: + op->jump = addr + target->v0; + case RL78_OP_TYPE_SYMBOL: + // TODO indirect call to symbol (CALL AX) + break; + default: + rz_warn_if_reached(); + break; + } + + if (op->type == RZ_ANALYSIS_OP_TYPE_CJMP) { + op->fail = addr + instr_size; + } +} + +static char *get_reg_profile(RzAnalysis *analysis) { + const char *p = + "=PC pc\n" + "=SP sp\n" + "=ZF z\n" + "=CF cy\n" + "=SN %s\n" // x8 on linux or android, x16 for the rest + // ABI: https://www.renesas.com/eu/en/document/mat/cc-rl-compiler-users-manual + "=A0 ax\n" + "=A1 bc\n" + "=A2 de\n" + // general-purpose registers + "gpr hl .16 0 0\n" + "gpr de .16 0 0\n" + "gpr bc .16 0 0\n" + "gpr ax .16 0 0\n" + "gpr h .8 0 0\n" + "gpr l .8 0 0\n" + "gpr d .8 0 0\n" + "gpr e .8 0 0\n" + "gpr b .8 0 0\n" + "gpr c .8 0 0\n" + "gpr a .8 0 0\n" + "gpr x .8 0 0\n" + + // flags + "flg psw .8 0 0 ie_z_rbs1_ac_rbs0_isp1_isp0_cy\n" + "flg ie .1 0 0 interrupt_enable\n" + "flg z .1 0 0 zero\n" + "flg rbs1 .1 0 0 register_bank_select_bit_1\n" + "flg ac .1 0 0 auxiliary_carry\n" // set if carry or borrow at bit 3 + "flg rbs0 .1 0 0 register_bank_select_bit_0\n" + "flg isp1 .1 0 0 in_service_priority_flags_bit_1\n" + "flg isp0 .1 0 0 in_service_priority_flags_bit_0\n" + "flg cy .1 0 0 carry\n"; + + return strdup(p); +} + +RzAnalysisPlugin rz_analysis_plugin_rl78 = { + .name = "rl78", + .desc = "Renesas RL78 analysis plugin", + .license = "LGPL3", + .arch = "rl78", + .bits = 16, + .op = &rl78_op, + .get_reg_profile = &get_reg_profile +}; + +#ifndef RZ_PLUGIN_INCORE +RZ_API RzLibStruct rizin_plugin = { + .type = RZ_LIB_TYPE_ANALYSIS, + .data = &rz_analysis_plugin_rl78, + .version = RZ_VERSION +}; +#endif diff --git a/librz/asm/arch/rl78/rl78.c b/librz/asm/arch/rl78/rl78.c new file mode 100644 index 00000000000..679790adcb5 --- /dev/null +++ b/librz/asm/arch/rl78/rl78.c @@ -0,0 +1,271 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#include "rl78.h" +#include "rl78_maps.h" +#include + +#define CHECK_BOUNDS(p, len) \ + if (*p >= len) { \ + return false; \ + } + +static bool parse_operand(RL78Operand RZ_INOUT *operand, size_t RZ_INOUT *next_byte_p, + const ut8 RZ_BORROW *buf, size_t buf_len); + +static inline bool optype_es_applies(RL78OperandType type); + +// used to decide whether an operand could resolve to a symbol +static inline bool final_value_known(RL78OperandType type); +static inline RL78Label addr_to_symbol(int addr); + +/** + * \brief Disassemble a byte sequence into an rl78_instr + * \param instr Resulting instruction + * \param byte_read Number of bytes disassembled + * \param buf Byte buffer + * \param buf_len Length of the buffer + * \return false if byte sequence does not represent a valid instruction + */ +bool rl78_dis(RL78Instr RZ_OUT *instr, size_t RZ_OUT *bytes_read, + const ut8 *buf, size_t buf_len) { + if (buf_len == 0) { + *bytes_read = 0; + return false; + } + + size_t next_byte_p = 0; + int byte = buf[next_byte_p++]; + + bool extension_addressing = false; + if (byte == 0x11) { + extension_addressing = true; + if (next_byte_p >= buf_len) { + *bytes_read = next_byte_p; + return false; + } + + byte = buf[next_byte_p++]; + } + + if (next_byte_p + 1 < buf_len) { + // MULHU, MULH... + if (byte == 0xCE && buf[next_byte_p] == 0xFB) { + switch (buf[next_byte_p + 1]) { + case 0x01: instr->operation = RL78_OPERATION_MULHU; break; + case 0x02: instr->operation = RL78_OPERATION_MULH; break; + case 0x03: instr->operation = RL78_OPERATION_DIVHU; break; + case 0x0B: instr->operation = RL78_OPERATION_DIVWU; break; + case 0x05: instr->operation = RL78_OPERATION_MACHU; break; + case 0x06: instr->operation = RL78_OPERATION_MACH; break; + default: break; + } + } + + // EI/DI aliases for set1 psw.7/clr1 psw.7 + if (byte == 0x71 && buf[next_byte_p + 1] == 0xFA) { + switch (buf[next_byte_p]) { + case 0x7A: instr->operation = RL78_OPERATION_EI; break; + case 0x7B: instr->operation = RL78_OPERATION_DI; break; + default: break; + } + } + + if (instr->operation != RL78_OPERATION_NONE) { + *bytes_read = next_byte_p + 2; + return true; + } + } + + // regular processing (get correct map, extract instruction and parse operands) + int map = 0; + switch (byte) { + case 0x31: + // 4th map + map = 3; + break; + case 0x61: + // 2nd map + map = 1; + break; + case 0x71: + // 3rd map + map = 2; + break; + default: + break; + } + + // get next byte if other map was chosen + if (map > 0) { + if (next_byte_p >= buf_len) { + *bytes_read = next_byte_p; + return false; + } + + byte = buf[next_byte_p++]; + } + + *instr = rl78_instr_maps[(map * 256) + byte]; + + // an empty slot was indexed + if (instr->operation == RL78_OPERATION_NONE) { + *bytes_read = next_byte_p; + return false; + } + + if (!parse_operand(&instr->op0, &next_byte_p, buf, buf_len) || + !parse_operand(&instr->op1, &next_byte_p, buf, buf_len)) { + *bytes_read = next_byte_p; + return false; + } + + if (extension_addressing) { + if (optype_es_applies(instr->op0.type)) { + instr->op0.flags |= RL78_OP_FLAG_ES; + } else if (optype_es_applies(instr->op1.type)) { + instr->op1.flags |= RL78_OP_FLAG_ES; + } + } + + *bytes_read = next_byte_p; + return true; +} + +static bool parse_operand(RL78Operand RZ_INOUT *operand, size_t RZ_INOUT *next_byte_p, + const ut8 RZ_BORROW *buf, size_t buf_len) { + switch (operand->type) { + // byte-sized operands + case RL78_OP_TYPE_IMMEDIATE_8: + case RL78_OP_TYPE_RELATIVE_ADDR_8: + case RL78_OP_TYPE_BASED_ADDR_8: + // already has value + if (operand->v1 != 0) { + return true; + } + + CHECK_BOUNDS(next_byte_p, buf_len); + + if (operand->type == RL78_OP_TYPE_BASED_ADDR_8) { + // write to v1 since v0 already has base register + operand->v1 = buf[*next_byte_p]; + } else { + operand->v0 = buf[*next_byte_p]; + } + (*next_byte_p)++; + + break; + + case RL78_OP_TYPE_SFR: + if (operand->v0 != 0) { + // already has value + return true; + } + + CHECK_BOUNDS(next_byte_p, buf_len); + + operand->v0 = 0xFFF00 + buf[*next_byte_p]; + (*next_byte_p)++; + + break; + + case RL78_OP_TYPE_SADDR: + CHECK_BOUNDS(next_byte_p, buf_len); + + operand->v0 = 0xFFE20 + buf[*next_byte_p]; + (*next_byte_p)++; + + break; + + // word-sized operands + case RL78_OP_TYPE_IMMEDIATE_16: + case RL78_OP_TYPE_ABSOLUTE_ADDR_16: + case RL78_OP_TYPE_RELATIVE_ADDR_16: + case RL78_OP_TYPE_BASED_ADDR_16: + CHECK_BOUNDS(next_byte_p, buf_len); + + int word = buf[*next_byte_p]; + (*next_byte_p)++; + + CHECK_BOUNDS(next_byte_p, buf_len); + + word |= (int)buf[*next_byte_p] << 8; + (*next_byte_p)++; + + if (operand->type == RL78_OP_TYPE_BASED_ADDR_16) { + // write to v1 since v0 already has base register + operand->v1 = word; + } else { + operand->v0 = word; + } + + break; + + // 20 bit + case RL78_OP_TYPE_ABSOLUTE_ADDR_20: + CHECK_BOUNDS(next_byte_p, buf_len); + + int val = buf[*next_byte_p]; + (*next_byte_p)++; + + CHECK_BOUNDS(next_byte_p, buf_len); + + val |= (int)buf[*next_byte_p] << 8; + (*next_byte_p)++; + + CHECK_BOUNDS(next_byte_p, buf_len); + + val |= (int)(buf[*next_byte_p] & 0xf) << 16; + (*next_byte_p)++; + + operand->v0 = val; + + break; + + default: // no need to get additional data (NONE, SYMBOL, ...) + break; + } + + if (final_value_known(operand->type)) { + // try resolving address to symbol for known fixed addresses + RL78Label symbol = addr_to_symbol(operand->v0); + if (rl78_symbol_valid(symbol)) { + operand->v0 = symbol; + } + } + + return true; +} + +static inline bool optype_es_applies(RL78OperandType type) { + return type == RL78_OP_TYPE_INDIRECT_ADDR || + type == RL78_OP_TYPE_BASED_ADDR_8 || + type == RL78_OP_TYPE_BASED_ADDR_16 || + type == RL78_OP_TYPE_ABSOLUTE_ADDR_16 || + type == RL78_OP_TYPE_BASED_INDEX_ADDR; +} + +static inline bool final_value_known(RL78OperandType type) { + return type == RL78_OP_TYPE_ABSOLUTE_ADDR_16 || + type == RL78_OP_TYPE_ABSOLUTE_ADDR_20 || + type == RL78_OP_TYPE_SFR || + type == RL78_OP_TYPE_SADDR; +} + +static inline RL78Label addr_to_symbol(int addr) { + switch (addr) { + // TODO add general-purpose registers + case 0xFFFF8: return RL78_SFR_SPL; + case 0xFFFF9: return RL78_SFR_SPH; + case 0xFFFFA: + return RL78_SFR_PSW; + // case 0xFB: (reserved) + case 0xFFFFC: return RL78_SFR_CS; + case 0xFFFFD: return RL78_SFR_ES; + case 0xFFFFE: return RL78_SFR_PMC; + case 0xFFFFF: return RL78_SFR_MEM; + default: + // invalid + return _RL78_SYMBOL_COUNT; + } +} diff --git a/librz/asm/arch/rl78/rl78.h b/librz/asm/arch/rl78/rl78.h new file mode 100644 index 00000000000..6ee98a467ca --- /dev/null +++ b/librz/asm/arch/rl78/rl78.h @@ -0,0 +1,15 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RL78_H +#define RL78_H + +#include "rl78_instr.h" + +#include +#include + +bool rl78_dis(RL78Instr RZ_OUT *instr, size_t RZ_OUT *bytes_read, + const ut8 *buf, size_t buf_len); + +#endif diff --git a/librz/asm/arch/rl78/rl78_instr.c b/librz/asm/arch/rl78/rl78_instr.c new file mode 100644 index 00000000000..73ae5ccc097 --- /dev/null +++ b/librz/asm/arch/rl78/rl78_instr.c @@ -0,0 +1,123 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#include "rl78_instr.h" + +#include +#include + +static const char *RL78_STRINGS_OPERATIONS[] = { + [RL78_OPERATION_ADD] = "add", + [RL78_OPERATION_ADDC] = "addc", + [RL78_OPERATION_ADDW] = "addw", + [RL78_OPERATION_AND] = "and", + [RL78_OPERATION_AND1] = "and1", + [RL78_OPERATION_BC] = "bc", + [RL78_OPERATION_BF] = "bf", + [RL78_OPERATION_BH] = "bh", + [RL78_OPERATION_BNC] = "bnc", + [RL78_OPERATION_BNH] = "bnh", + [RL78_OPERATION_BNZ] = "bnz", + [RL78_OPERATION_BR] = "br", + [RL78_OPERATION_BRK] = "brk", + [RL78_OPERATION_BT] = "bt", + [RL78_OPERATION_BTCLR] = "btclr", + [RL78_OPERATION_BZ] = "bz", + [RL78_OPERATION_CALL] = "call", + [RL78_OPERATION_CALLT] = "callt", + [RL78_OPERATION_CLRB] = "clrb", + [RL78_OPERATION_CLRW] = "clrw", + [RL78_OPERATION_CLR1] = "clr1", + [RL78_OPERATION_CMP] = "cmp", + [RL78_OPERATION_CMPS] = "cmps", + [RL78_OPERATION_CMPW] = "cmpw", + [RL78_OPERATION_CMP0] = "cmp0", + [RL78_OPERATION_DEC] = "dec", + [RL78_OPERATION_DECW] = "decw", + [RL78_OPERATION_DI] = "di", + [RL78_OPERATION_DIVHU] = "divhu", + [RL78_OPERATION_DIVWU] = "divwu", + [RL78_OPERATION_EI] = "ei", + [RL78_OPERATION_HALT] = "halt", + [RL78_OPERATION_INC] = "inc", + [RL78_OPERATION_INCW] = "incw", + [RL78_OPERATION_MACH] = "mach", + [RL78_OPERATION_MACHU] = "machu", + [RL78_OPERATION_MOV] = "mov", + [RL78_OPERATION_MOVS] = "movs", + [RL78_OPERATION_MOVW] = "movw", + [RL78_OPERATION_MOV1] = "mov1", + [RL78_OPERATION_MULH] = "mulh", + [RL78_OPERATION_MULHU] = "mulhu", + [RL78_OPERATION_MULU] = "mulu", + [RL78_OPERATION_NOP] = "nop", + [RL78_OPERATION_NOT1] = "not1", + [RL78_OPERATION_ONEB] = "oneb", + [RL78_OPERATION_ONEW] = "onew", + [RL78_OPERATION_OR] = "or", + [RL78_OPERATION_OR1] = "or1", + [RL78_OPERATION_POP] = "pop", + [RL78_OPERATION_PUSH] = "push", + [RL78_OPERATION_RET] = "ret", + [RL78_OPERATION_RETB] = "retb", + [RL78_OPERATION_RETI] = "reti", + [RL78_OPERATION_ROL] = "rol", + [RL78_OPERATION_ROLC] = "rolc", + [RL78_OPERATION_ROLWC] = "rolwc", + [RL78_OPERATION_ROR] = "ror", + [RL78_OPERATION_RORC] = "rorc", + [RL78_OPERATION_SAR] = "sar", + [RL78_OPERATION_SARW] = "sarw", + [RL78_OPERATION_SEL] = "sel", + [RL78_OPERATION_SET1] = "set1", + [RL78_OPERATION_SHL] = "shl", + [RL78_OPERATION_SHLW] = "shlw", + [RL78_OPERATION_SHR] = "shr", + [RL78_OPERATION_SHRW] = "shrw", + [RL78_OPERATION_SKC] = "skc", + [RL78_OPERATION_SKH] = "skh", + [RL78_OPERATION_SKNC] = "sknc", + [RL78_OPERATION_SKNH] = "sknh", + [RL78_OPERATION_SKNZ] = "sknz", + [RL78_OPERATION_SKZ] = "skz", + [RL78_OPERATION_STOP] = "stop", + [RL78_OPERATION_SUB] = "sub", + [RL78_OPERATION_SUBC] = "subc", + [RL78_OPERATION_SUBW] = "subw", + [RL78_OPERATION_XCH] = "xch", + [RL78_OPERATION_XCHW] = "xchw", + [RL78_OPERATION_XOR] = "xor", + [RL78_OPERATION_XOR1] = "xor1", +}; + +bool rl78_instr_to_string(RzStrBuf RZ_OUT *dst, const RL78Instr RZ_BORROW *instr) { + rz_return_val_if_fail(instr->operation > 0 && + instr->operation < _RL78_OPERATION_COUNT, + false); + + // 16 characters suffice for each operand + RzStrBuf buf_op0, buf_op1; + bool has_op0 = instr->op0.type != RL78_OP_TYPE_NONE; + bool has_op1 = instr->op1.type != RL78_OP_TYPE_NONE; + + rz_return_val_if_fail(!has_op0 || rl78_operand_to_string(&buf_op0, &instr->op0), + false); + + rz_return_val_if_fail(!has_op1 || rl78_operand_to_string(&buf_op1, &instr->op1), + false); + + if (has_op0 && has_op1) { + rz_strbuf_appendf(dst, "%s %s, %s", + RL78_STRINGS_OPERATIONS[instr->operation], + buf_op0.buf, buf_op1.buf); + } else if (has_op0) { + rz_strbuf_appendf(dst, "%s %s", + RL78_STRINGS_OPERATIONS[instr->operation], + buf_op0.buf); + } else { + rz_strbuf_appendf(dst, "%s", + RL78_STRINGS_OPERATIONS[instr->operation]); + } + + return true; +} diff --git a/librz/asm/arch/rl78/rl78_instr.h b/librz/asm/arch/rl78/rl78_instr.h new file mode 100644 index 00000000000..60f58b18966 --- /dev/null +++ b/librz/asm/arch/rl78/rl78_instr.h @@ -0,0 +1,116 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RL78_INSTR_H +#define RL78_INSTR_H + +#include "rl78_operand.h" + +#include +#include + +typedef enum RL78Operation { + RL78_OPERATION_NONE, + + RL78_OPERATION_ADD, + RL78_OPERATION_ADDC, + RL78_OPERATION_ADDW, + RL78_OPERATION_AND, + RL78_OPERATION_AND1, + RL78_OPERATION_BC, + RL78_OPERATION_BF, + RL78_OPERATION_BH, + RL78_OPERATION_BNC, + RL78_OPERATION_BNH, + RL78_OPERATION_BNZ, + RL78_OPERATION_BR, + RL78_OPERATION_BRK, + RL78_OPERATION_BT, + RL78_OPERATION_BTCLR, + RL78_OPERATION_BZ, + RL78_OPERATION_CALL, + RL78_OPERATION_CALLT, + RL78_OPERATION_CLRB, + RL78_OPERATION_CLRW, + RL78_OPERATION_CLR1, + RL78_OPERATION_CMP, + RL78_OPERATION_CMPS, + RL78_OPERATION_CMPW, + RL78_OPERATION_CMP0, + RL78_OPERATION_DEC, + RL78_OPERATION_DECW, + RL78_OPERATION_DI, + RL78_OPERATION_DIVHU, + RL78_OPERATION_DIVWU, + RL78_OPERATION_EI, + RL78_OPERATION_HALT, + RL78_OPERATION_INC, + RL78_OPERATION_INCW, + RL78_OPERATION_MACH, + RL78_OPERATION_MACHU, + RL78_OPERATION_MOV, + RL78_OPERATION_MOVS, + RL78_OPERATION_MOVW, + RL78_OPERATION_MOV1, + RL78_OPERATION_MULH, + RL78_OPERATION_MULHU, + RL78_OPERATION_MULU, + RL78_OPERATION_NOP, + RL78_OPERATION_NOT1, + RL78_OPERATION_ONEB, + RL78_OPERATION_ONEW, + RL78_OPERATION_OR, + RL78_OPERATION_OR1, + RL78_OPERATION_POP, + RL78_OPERATION_PUSH, + RL78_OPERATION_RET, + RL78_OPERATION_RETB, + RL78_OPERATION_RETI, + RL78_OPERATION_ROL, + RL78_OPERATION_ROLC, + RL78_OPERATION_ROLWC, + RL78_OPERATION_ROR, + RL78_OPERATION_RORC, + RL78_OPERATION_SAR, + RL78_OPERATION_SARW, + RL78_OPERATION_SEL, + RL78_OPERATION_SET1, + RL78_OPERATION_SHL, + RL78_OPERATION_SHLW, + RL78_OPERATION_SHR, + RL78_OPERATION_SHRW, + RL78_OPERATION_SKC, + RL78_OPERATION_SKH, + RL78_OPERATION_SKNC, + RL78_OPERATION_SKNH, + RL78_OPERATION_SKNZ, + RL78_OPERATION_SKZ, + RL78_OPERATION_STOP, + RL78_OPERATION_SUB, + RL78_OPERATION_SUBC, + RL78_OPERATION_SUBW, + RL78_OPERATION_XCH, + RL78_OPERATION_XCHW, + RL78_OPERATION_XOR, + RL78_OPERATION_XOR1, + + _RL78_OPERATION_COUNT +} RL78Operation; + +typedef struct RL78Instr { + RL78Operand op0; + RL78Operand op1; + + RL78Operation operation; +} RL78Instr; + +/** + * \brief Convert an RL78 instruction to a string + * \param dst Caller-supplied character buffer to print into + * \param n Size of dst + * \param operand RL78 instruction to be printed + * \return false On failure + */ +bool rl78_instr_to_string(RzStrBuf RZ_OUT *dst, const RL78Instr RZ_BORROW *instr); + +#endif diff --git a/librz/asm/arch/rl78/rl78_maps.c b/librz/asm/arch/rl78/rl78_maps.c new file mode 100644 index 00000000000..b5aac04f0e1 --- /dev/null +++ b/librz/asm/arch/rl78/rl78_maps.c @@ -0,0 +1,2661 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#include "rl78_maps.h" + +/* + * The 'User's Manual: Software' for the RL78 Family arranges instructions in + * four instruction maps, each indexed by an unsigned byte. Thus, the entry at + * index [0xXYZ] corresponds to entry YZ of instruction map (X + 1). Empty + * positions are left out + */ + +RL78Instr rl78_instr_maps[4 * 256] = { + // map 0 + // 0x000-0x0f + [0x000] = { .operation = RL78_OPERATION_NOP }, + [0x001] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_ADDW }, + [0x002] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_ADDW }, + [0x003] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_ADDW }, + [0x004] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_ADDW }, + [0x005] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_ADDW }, + [0x006] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_ADDW }, + [0x007] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_ADDW }, + [0x008] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_XCH }, + [0x009] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_MOV }, + [0x00A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_ADD }, + [0x00B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_ADD }, + [0x00C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_ADD }, + [0x00D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_ADD }, + [0x00E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_ADD }, + [0x00F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_ADD }, + + // 0x010-0x01f + [0x010] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_CR_SP }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_ADDW }, + [0x012] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x013] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_MOVW }, + [0x014] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x015] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_MOVW }, + [0x016] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x017] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_MOVW }, + [0x018] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x019] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x01A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_ADDC }, + [0x01B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_ADDC }, + [0x01C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_ADDC }, + [0x01D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_ADDC }, + [0x01E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_ADDC }, + [0x01F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_ADDC }, + + // 0x020-0x02f + [0x020] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_CR_SP }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_SUBW }, + [0x022] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_SUBW }, + [0x023] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_SUBW }, + [0x024] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_SUBW }, + [0x025] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_SUBW }, + [0x026] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_SUBW }, + [0x027] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_SUBW }, + [0x028] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x029] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_MOV }, + [0x02A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_SUB }, + [0x02B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_SUB }, + [0x02C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_SUB }, + [0x02D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_SUB }, + [0x02E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_SUB }, + [0x02F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_SUB }, + + // 0x030-0x03f + [0x030] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x032] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x033] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_XCHW }, + [0x034] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x035] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_XCHW }, + [0x036] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x037] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_XCHW }, + [0x038] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x039] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x03A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_SUBC }, + [0x03B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_SUBC }, + [0x03C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_SUBC }, + [0x03D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_SUBC }, + [0x03E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_SUBC }, + [0x03F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_SUBC }, + + // 0x040-0x04f + [0x040] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_CMP }, + [0x041] = { { .type = RL78_OP_TYPE_SFR, .v0 = RL78_SFR_ES }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x042] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_CMPW }, + [0x043] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_CMPW }, + [0x044] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_CMPW }, + [0x045] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_CMPW }, + [0x046] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_CMPW }, + [0x047] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_CMPW }, + [0x048] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x049] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_MOV }, + [0x04A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_CMP }, + [0x04B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_CMP }, + [0x04C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_CMP }, + [0x04D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_CMP }, + [0x04E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_CMP }, + [0x04F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_CMP }, + + // 0x050-0x05f + [0x050] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x051] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x052] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x053] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x054] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x055] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x056] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x057] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x058] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x059] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_MOVW }, + [0x05A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_AND }, + [0x05B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_AND }, + [0x05C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_AND }, + [0x05D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_AND }, + [0x05E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_AND }, + [0x05F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_AND }, + + // 0x060-0x06f + [0x060] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_MOV }, + [0x062] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_MOV }, + [0x063] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_MOV }, + [0x064] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_MOV }, + [0x065] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_MOV }, + [0x066] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_MOV }, + [0x067] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_MOV }, + [0x068] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x069] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_MOVW }, + [0x06A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_OR }, + [0x06B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_OR }, + [0x06C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_OR }, + [0x06D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_OR }, + [0x06E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_OR }, + [0x06F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_OR }, + + // 0x070-0x07f + [0x070] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x072] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x073] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x074] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x075] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x076] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x077] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x078] = { { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x079] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_16, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_MOVW }, + [0x07A] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_XOR }, + [0x07B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_XOR }, + [0x07C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { + .type = RL78_OP_TYPE_IMMEDIATE_8, + }, + .operation = RL78_OPERATION_XOR }, + [0x07D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_XOR }, + [0x07E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_XOR }, + [0x07F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_XOR }, + + // 0x080-0x08f + [0x080] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_INC }, + [0x081] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_INC }, + [0x082] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_INC }, + [0x083] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_INC }, + [0x084] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_INC }, + [0x085] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_INC }, + [0x086] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_INC }, + [0x087] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_INC }, + [0x088] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_CR_SP }, + .operation = RL78_OPERATION_MOV }, + [0x089] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_MOV }, + [0x08A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_MOV }, + [0x08B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_MOV }, + [0x08C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_MOV }, + [0x08D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOV }, + [0x08E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SFR }, + .operation = RL78_OPERATION_MOV }, + [0x08F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOV }, + + // 0x090-0x09f + [0x090] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_DEC }, + [0x091] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_DEC }, + [0x092] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_DEC }, + [0x093] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_DEC }, + [0x094] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_DEC }, + [0x095] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_DEC }, + [0x096] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_DEC }, + [0x097] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_DEC }, + [0x098] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_CR_SP }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x099] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x09A] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x09B] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x09C] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x09D] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x09E] = { { .type = RL78_OP_TYPE_SFR }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x09F] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + + // 0x0A0-0x0af + [0x0A0] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_INC }, + [0x0A1] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_INCW }, + [0x0A2] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_INCW }, + [0x0A3] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_INCW }, + [0x0A4] = { { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_INC }, + [0x0A5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_INCW }, + [0x0A6] = { { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_INCW }, + [0x0A7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_INCW }, + [0x0A8] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_CR_SP }, + .operation = RL78_OPERATION_MOVW }, + [0x0A9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_MOVW }, + [0x0AA] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_MOVW }, + [0x0AB] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_MOVW }, + [0x0AC] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_MOVW }, + [0x0AD] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOVW }, + [0x0AE] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_SFR }, + .operation = RL78_OPERATION_MOVW }, + [0x0AF] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOVW }, + + // 0x0B0-0x0bf + [0x0B0] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_DEC }, + [0x0B1] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_DECW }, + [0x0B2] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_DECW }, + [0x0B3] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_DECW }, + [0x0B4] = { { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_DEC }, + [0x0B5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_DECW }, + [0x0B6] = { { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_DECW }, + [0x0B7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_DECW }, + [0x0B8] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_CR_SP }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x0B9] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x0BA] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x0BB] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x0BC] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x0BD] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x0BE] = { { .type = RL78_OP_TYPE_SFR }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + [0x0BF] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_MOVW }, + + // 0x0C0-0x0cf + [0x0C0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_POP }, + [0x0C1] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_PUSH }, + [0x0C2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_POP }, + [0x0C3] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_PUSH }, + [0x0C4] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_POP }, + [0x0C5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_PUSH }, + [0x0C6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_POP }, + [0x0C7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_PUSH }, + [0x0C8] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_CR_SP }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x0C9] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x0CA] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x0CB] = { { .type = RL78_OP_TYPE_SFR }, + { .type = RL78_OP_TYPE_IMMEDIATE_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x0CC] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x0CD] = { { .type = RL78_OP_TYPE_SADDR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x0CE] = { { .type = RL78_OP_TYPE_SFR }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + [0x0CF] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + { .type = RL78_OP_TYPE_IMMEDIATE_8 }, + .operation = RL78_OPERATION_MOV }, + + // 0X0D0-0x0df + [0x0D0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_CMP0 }, + [0x0D1] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP0 }, + [0x0D2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_CMP0 }, + [0x0D3] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_CMP0 }, + [0x0D4] = { { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_CMP0 }, + [0x0D5] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_CMP0 }, + [0x0D6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_MULU }, + [0x0D7] = { .operation = RL78_OPERATION_RET }, + [0x0D8] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOV }, + [0x0D9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOV }, + [0x0DA] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOVW }, + [0x0DB] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x0DC] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BC }, + [0x0DD] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BZ }, + [0x0DE] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BNC }, + [0x0DF] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BNZ }, + + // 0X0E0-0x0ef + [0x0E0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_ONEB }, + [0x0E1] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ONEB }, + [0x0E2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_ONEB }, + [0x0E3] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_ONEB }, + [0x0E4] = { { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_ONEB }, + [0x0E5] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_ONEB }, + [0x0E6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_ONEW }, + [0x0E7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_ONEW }, + [0x0E8] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOV }, + [0x0E9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOV }, + [0x0EA] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOVW }, + [0x0EB] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x0EC] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_20 }, + .operation = RL78_OPERATION_BR }, + [0x0ED] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_BR }, + [0x0EE] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_16 }, + .operation = RL78_OPERATION_BR }, + [0x0EF] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BR }, + + // 0X0F0-0x0ff + [0x0F0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_CLRB }, + [0x0F1] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CLRB }, + [0x0F2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_CLRB }, + [0x0F3] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_CLRB }, + [0x0F4] = { { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_CLRB }, + [0x0F5] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_CLRB }, + [0x0F6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_CLRW }, + [0x0F7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_CLRW }, + [0x0F8] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOV }, + [0x0F9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOV }, + [0x0FA] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOVW }, + [0x0FB] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_MOVW }, + [0x0FC] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_20 }, + .operation = RL78_OPERATION_CALL }, + [0x0FD] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_CALL }, + [0x0FE] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_16 }, + .operation = RL78_OPERATION_CALL }, + + // map 1 + // 0x100-0x10f + [0x100] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x101] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x102] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x103] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x104] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x105] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x106] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x107] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADD }, + [0x108] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_ADD }, + [0x109] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_ADDW }, + [0x10A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_ADD }, + [0x10B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_ADD }, + [0x10C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_ADD }, + [0x10D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_ADD }, + [0x10E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_ADD }, + [0x10F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_ADD }, + + // 0x110-0x11f + [0x110] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x111] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x112] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x113] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x114] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x115] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x116] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x117] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_ADDC }, + [0x118] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_ADDC }, + [0x11A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_ADDC }, + [0x11B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_ADDC }, + [0x11C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_ADDC }, + [0x11D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_ADDC }, + [0x11E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_ADDC }, + [0x11F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_ADDC }, + + // 0x120-0x12f + [0x120] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x121] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x122] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x123] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x124] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x125] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x126] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x127] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUB }, + [0x128] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_SUB }, + [0x129] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_SUBW }, + [0x12A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_SUB }, + [0x12B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_SUB }, + [0x12C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_SUB }, + [0x12D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_SUB }, + [0x12E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_SUB }, + [0x12F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_SUB }, + + // 0x130-0x13f + [0x130] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x131] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x132] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x133] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x134] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x135] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x136] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x137] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_SUBC }, + [0x138] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_SUBC }, + [0x13A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_SUBC }, + [0x13B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_SUBC }, + [0x13C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_SUBC }, + [0x13D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_SUBC }, + [0x13E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_SUBC }, + [0x13F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_SUBC }, + + // 0x140-0x14f + [0x140] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x141] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x142] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x143] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x144] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x145] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x146] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x147] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_CMP }, + [0x148] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_CMP }, + [0x149] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_CMPW }, + [0x14A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_CMP }, + [0x14B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_CMP }, + [0x14C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_CMP }, + [0x14D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_CMP }, + [0x14E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_CMP }, + [0x14F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_CMP }, + + // 0x150-0x15f + [0x150] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x151] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x152] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x153] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x154] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x155] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x156] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x157] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_AND }, + [0x158] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_AND }, + [0x159] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_INC }, + [0x15A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_AND }, + [0x15B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_AND }, + [0x15C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_AND }, + [0x15D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_AND }, + [0x15E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_AND }, + [0x15F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_AND }, + + // 0x160-0x16f + [0x160] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x161] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x162] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x163] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x164] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x165] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x166] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x167] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_OR }, + [0x168] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_OR }, + [0x169] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_DEC }, + [0x16A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_OR }, + [0x16B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_OR }, + [0x16C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_OR }, + [0x16D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_OR }, + [0x16E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_OR }, + [0x16F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_OR }, + + // 0x170-0x17f + [0x170] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x171] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x172] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x173] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x174] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x175] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x176] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x177] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_XOR }, + [0x178] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_XOR }, + [0x179] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_INCW }, + [0x17A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_XOR }, + [0x17B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_XOR }, + [0x17C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_XOR }, + [0x17D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_XOR }, + [0x17E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_XOR }, + [0x17F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_XOR }, + + // 0x180-0x18f + [0x180] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_ADD }, + [0x182] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_ADD }, + [0x184] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0080 }, + .operation = RL78_OPERATION_CALLT }, + [0x185] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0090 }, + .operation = RL78_OPERATION_CALLT }, + [0x186] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00A0 }, + .operation = RL78_OPERATION_CALLT }, + [0x187] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00B0 }, + .operation = RL78_OPERATION_CALLT }, + [0x189] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_DECW }, + [0x18A] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + .operation = RL78_OPERATION_XCH }, + [0x18B] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + .operation = RL78_OPERATION_XCH }, + [0x18C] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_E }, + .operation = RL78_OPERATION_XCH }, + [0x18D] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_D }, + .operation = RL78_OPERATION_XCH }, + [0x18E] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_L }, + .operation = RL78_OPERATION_XCH }, + [0x18F] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_H }, + .operation = RL78_OPERATION_XCH }, + + // 0x190-0x19f + [0x190] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_ADDC }, + [0x192] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_ADDC }, + [0x194] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0082 }, + .operation = RL78_OPERATION_CALLT }, + [0x195] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0092 }, + .operation = RL78_OPERATION_CALLT }, + [0x196] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00A2 }, + .operation = RL78_OPERATION_CALLT }, + [0x197] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00B2 }, + .operation = RL78_OPERATION_CALLT }, + + // 0x1a0-0x1af + [0x1a0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_SUB }, + [0x1a2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_SUB }, + [0x1a4] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0084 }, + .operation = RL78_OPERATION_CALLT }, + [0x1a5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0094 }, + .operation = RL78_OPERATION_CALLT }, + [0x1a6] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00A4 }, + .operation = RL78_OPERATION_CALLT }, + [0x1a7] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00B4 }, + .operation = RL78_OPERATION_CALLT }, + [0x1a8] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_XCH }, + [0x1a9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_XCH }, + [0x1aa] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16 }, + .operation = RL78_OPERATION_XCH }, + [0x1ab] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_SFR }, + .operation = RL78_OPERATION_XCH }, + [0x1ac] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_XCH }, + [0x1ad] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_XCH }, + [0x1ae] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_XCH }, + [0x1af] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_XCH }, + + // 0x1b0-0x1bf + [0x1b0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_SUBC }, + [0x1b2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_SUBC }, + [0x1b4] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0086 }, + .operation = RL78_OPERATION_CALLT }, + [0x1b5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0096 }, + .operation = RL78_OPERATION_CALLT }, + [0x1b6] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00A6 }, + .operation = RL78_OPERATION_CALLT }, + [0x1b7] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00B6 }, + .operation = RL78_OPERATION_CALLT }, + [0x1b8] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_SFR_ES }, + { .type = RL78_OP_TYPE_SADDR }, + .operation = RL78_OPERATION_MOV }, + [0x1b9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_XCH }, + + // 0x1c0-0x1cf + [0x1c0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_CMP }, + [0x1c2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_CMP }, + [0x1c3] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BH }, + [0x1c4] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0088 }, + .operation = RL78_OPERATION_CALLT }, + [0x1c5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x0098 }, + .operation = RL78_OPERATION_CALLT }, + [0x1c6] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00A8 }, + .operation = RL78_OPERATION_CALLT }, + [0x1c7] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00B8 }, + .operation = RL78_OPERATION_CALLT }, + [0x1c8] = { .operation = RL78_OPERATION_SKC }, + [0x1c9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_MOV }, + [0x1ca] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_CALL }, + [0x1cb] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + .operation = RL78_OPERATION_BR }, + [0x1cc] = { .operation = RL78_OPERATION_BRK }, + [0x1cd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_SFR_PSW }, + .operation = RL78_OPERATION_POP }, + [0x1ce] = { { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + .operation = RL78_OPERATION_MOVS }, + [0x1cf] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_RB_RB0 }, + .operation = RL78_OPERATION_SEL }, + + // 0x1d0-0x1df + [0x1d0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_AND }, + [0x1d2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_AND }, + [0x1d3] = { { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BNH }, + [0x1d4] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x008A }, + .operation = RL78_OPERATION_CALLT }, + [0x1d5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x009A }, + .operation = RL78_OPERATION_CALLT }, + [0x1d6] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00AA }, + .operation = RL78_OPERATION_CALLT }, + [0x1d7] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00BA }, + .operation = RL78_OPERATION_CALLT }, + [0x1d8] = { .operation = RL78_OPERATION_SKNC }, + [0x1d9] = { { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x1da] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + .operation = RL78_OPERATION_CALL }, + [0x1db] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_ROR }, + [0x1dc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_ROLC }, + [0x1dd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_SFR_PSW }, + .operation = RL78_OPERATION_PUSH }, + [0x1de] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_X }, + { .type = RL78_OP_TYPE_BASED_ADDR_8, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_CMPS }, + [0x1df] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_RB_RB1 }, + .operation = RL78_OPERATION_SEL }, + + // 0x1e0-0x1ef + [0x1e0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_OR }, + [0x1e2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_OR }, + [0x1e3] = { .operation = RL78_OPERATION_SKH }, + [0x1e4] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x008C }, + .operation = RL78_OPERATION_CALLT }, + [0x1e5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x009C }, + .operation = RL78_OPERATION_CALLT }, + [0x1e6] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00AC }, + .operation = RL78_OPERATION_CALLT }, + [0x1e7] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00BC }, + .operation = RL78_OPERATION_CALLT }, + [0x1e8] = { .operation = RL78_OPERATION_SKZ }, + [0x1e9] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_MOV }, + [0x1ea] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_DE }, + .operation = RL78_OPERATION_CALL }, + [0x1eb] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_ROL }, + [0x1ec] = { .operation = RL78_OPERATION_RETB }, + [0x1ed] = { .operation = RL78_OPERATION_HALT }, + [0x1ee] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_ROLWC }, + [0x1ef] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_RB_RB2 }, + .operation = RL78_OPERATION_SEL }, + + // 0x1f0-0x1ff + [0x1f0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_B }, + .operation = RL78_OPERATION_XOR }, + [0x1f2] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + .operation = RL78_OPERATION_XOR }, + [0x1f3] = { .operation = RL78_OPERATION_SKNH }, + [0x1f4] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x008E }, + .operation = RL78_OPERATION_CALLT }, + [0x1f5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x009E }, + .operation = RL78_OPERATION_CALLT }, + [0x1f6] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00AE }, + .operation = RL78_OPERATION_CALLT }, + [0x1f7] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .v0 = 0x00BE }, + .operation = RL78_OPERATION_CALLT }, + [0x1f8] = { .operation = RL78_OPERATION_SKNZ }, + [0x1f9] = { { .type = RL78_OP_TYPE_BASED_INDEX_ADDR, .v0 = RL78_GPR_HL, .v1 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + .operation = RL78_OPERATION_MOV }, + [0x1fa] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_HL }, + .operation = RL78_OPERATION_CALL }, + [0x1fb] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_RORC }, + [0x1fc] = { .operation = RL78_OPERATION_RETI }, + [0x1fd] = { .operation = RL78_OPERATION_STOP }, + [0x1fe] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_ROLWC }, + [0x1ff] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_RB_RB3 }, + .operation = RL78_OPERATION_SEL }, + + // map 2 + // 0x200-0x20f + [0x200] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_SET1 }, + [0x201] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x202] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_SET1 }, + [0x203] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_CLR1 }, + [0x204] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_MOV1 }, + [0x205] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_AND1 }, + [0x206] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_OR1 }, + [0x207] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_XOR1 }, + [0x208] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_CLR1 }, + [0x209] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x20a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_SET1 }, + [0x20b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_CLR1 }, + [0x20c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_MOV1 }, + [0x20d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_AND1 }, + [0x20e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_OR1 }, + [0x20f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x210-0x21f + [0x210] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_SET1 }, + [0x211] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x212] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_SET1 }, + [0x213] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_CLR1 }, + [0x214] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_MOV1 }, + [0x215] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_AND1 }, + [0x216] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_OR1 }, + [0x217] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_XOR1 }, + [0x218] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_CLR1 }, + [0x219] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x21a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_SET1 }, + [0x21b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_CLR1 }, + [0x21c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_MOV1 }, + [0x21d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_AND1 }, + [0x21e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_OR1 }, + [0x21f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x220-0x22f + [0x220] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_SET1 }, + [0x221] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x222] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_SET1 }, + [0x223] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_CLR1 }, + [0x224] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_MOV1 }, + [0x225] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_AND1 }, + [0x226] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_OR1 }, + [0x227] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_XOR1 }, + [0x228] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_CLR1 }, + [0x229] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x22a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_SET1 }, + [0x22b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_CLR1 }, + [0x22c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_MOV1 }, + [0x22d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_AND1 }, + [0x22e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_OR1 }, + [0x22f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x230-0x23f + [0x230] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_SET1 }, + [0x231] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x232] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_SET1 }, + [0x233] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_CLR1 }, + [0x234] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_MOV1 }, + [0x235] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_AND1 }, + [0x236] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_OR1 }, + [0x237] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_XOR1 }, + [0x238] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_CLR1 }, + [0x239] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x23a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_SET1 }, + [0x23b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_CLR1 }, + [0x23c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_MOV1 }, + [0x23d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_AND1 }, + [0x23e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_OR1 }, + [0x23f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x240-0x24f + [0x240] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_SET1 }, + [0x241] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x242] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_SET1 }, + [0x243] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_CLR1 }, + [0x244] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_MOV1 }, + [0x245] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_AND1 }, + [0x246] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_OR1 }, + [0x247] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_XOR1 }, + [0x248] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_CLR1 }, + [0x249] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x24a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_SET1 }, + [0x24b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_CLR1 }, + [0x24c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_MOV1 }, + [0x24d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_AND1 }, + [0x24e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_OR1 }, + [0x24f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x250-0x25f + [0x250] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_SET1 }, + [0x251] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x252] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_SET1 }, + [0x253] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_CLR1 }, + [0x254] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_MOV1 }, + [0x255] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_AND1 }, + [0x256] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_OR1 }, + [0x257] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_XOR1 }, + [0x258] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_CLR1 }, + [0x259] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x25a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_SET1 }, + [0x25b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_CLR1 }, + [0x25c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_MOV1 }, + [0x25d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_AND1 }, + [0x25e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_OR1 }, + [0x25f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x260-0x26f + [0x260] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_SET1 }, + [0x261] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x262] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_SET1 }, + [0x263] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_CLR1 }, + [0x264] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_MOV1 }, + [0x265] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_AND1 }, + [0x266] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_OR1 }, + [0x267] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_XOR1 }, + [0x268] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_CLR1 }, + [0x269] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x26a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_SET1 }, + [0x26b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_CLR1 }, + [0x26c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_MOV1 }, + [0x26d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_AND1 }, + [0x26e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_OR1 }, + [0x26f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x270-0x27f + [0x270] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_SET1 }, + [0x271] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x272] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_SET1 }, + [0x273] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_CLR1 }, + [0x274] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_MOV1 }, + [0x275] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_AND1 }, + [0x276] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_OR1 }, + [0x277] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_XOR1 }, + [0x278] = { { .type = RL78_OP_TYPE_ABSOLUTE_ADDR_16, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_CLR1 }, + [0x279] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x27a] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_SET1 }, + [0x27b] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_CLR1 }, + [0x27c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_MOV1 }, + [0x27d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_AND1 }, + [0x27e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_OR1 }, + [0x27f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x280] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_SET1 }, + [0x281] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x282] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + .operation = RL78_OPERATION_SET1 }, + [0x283] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + .operation = RL78_OPERATION_CLR1 }, + [0x284] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + .operation = RL78_OPERATION_MOV1 }, + [0x285] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + .operation = RL78_OPERATION_AND1 }, + [0x286] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + .operation = RL78_OPERATION_OR1 }, + [0x287] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + .operation = RL78_OPERATION_XOR1 }, + [0x288] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_CLR1 }, + [0x289] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x28a] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + .operation = RL78_OPERATION_SET1 }, + [0x28b] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + .operation = RL78_OPERATION_CLR1 }, + [0x28c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + .operation = RL78_OPERATION_MOV1 }, + [0x28d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + .operation = RL78_OPERATION_AND1 }, + [0x28e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + .operation = RL78_OPERATION_OR1 }, + [0x28f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x291] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x292] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + .operation = RL78_OPERATION_SET1 }, + [0x293] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + .operation = RL78_OPERATION_CLR1 }, + [0x294] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + .operation = RL78_OPERATION_MOV1 }, + [0x295] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + .operation = RL78_OPERATION_AND1 }, + [0x296] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + .operation = RL78_OPERATION_OR1 }, + [0x297] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + .operation = RL78_OPERATION_XOR1 }, + [0x299] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x29a] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + .operation = RL78_OPERATION_SET1 }, + [0x29b] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + .operation = RL78_OPERATION_CLR1 }, + [0x29c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + .operation = RL78_OPERATION_MOV1 }, + [0x29d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + .operation = RL78_OPERATION_AND1 }, + [0x29e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + .operation = RL78_OPERATION_OR1 }, + [0x29f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x2a1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2a2] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + .operation = RL78_OPERATION_SET1 }, + [0x2a3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2a4] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2a5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + .operation = RL78_OPERATION_AND1 }, + [0x2a6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + .operation = RL78_OPERATION_OR1 }, + [0x2a7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + .operation = RL78_OPERATION_XOR1 }, + [0x2a9] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2aa] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + .operation = RL78_OPERATION_SET1 }, + [0x2ab] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2ac] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2ad] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + .operation = RL78_OPERATION_AND1 }, + [0x2ae] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + .operation = RL78_OPERATION_OR1 }, + [0x2af] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x2b1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2b2] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + .operation = RL78_OPERATION_SET1 }, + [0x2b3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2b4] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2b5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + .operation = RL78_OPERATION_AND1 }, + [0x2b6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + .operation = RL78_OPERATION_OR1 }, + [0x2b7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + .operation = RL78_OPERATION_XOR1 }, + [0x2b9] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2ba] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + .operation = RL78_OPERATION_SET1 }, + [0x2bb] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2bc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2bd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + .operation = RL78_OPERATION_AND1 }, + [0x2be] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + .operation = RL78_OPERATION_OR1 }, + [0x2bf] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x2c0] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_NOT1 }, + [0x2c1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2c2] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + .operation = RL78_OPERATION_SET1 }, + [0x2c3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2c4] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2c5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + .operation = RL78_OPERATION_AND1 }, + [0x2c6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + .operation = RL78_OPERATION_OR1 }, + [0x2c7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + .operation = RL78_OPERATION_XOR1 }, + [0x2c9] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2ca] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + .operation = RL78_OPERATION_SET1 }, + [0x2cb] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2cc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2cd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + .operation = RL78_OPERATION_AND1 }, + [0x2ce] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + .operation = RL78_OPERATION_OR1 }, + [0x2cf] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x2d1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2d2] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + .operation = RL78_OPERATION_SET1 }, + [0x2d3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2d4] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2d5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + .operation = RL78_OPERATION_AND1 }, + [0x2d6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + .operation = RL78_OPERATION_OR1 }, + [0x2d7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + .operation = RL78_OPERATION_XOR1 }, + [0x2d9] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2da] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + .operation = RL78_OPERATION_SET1 }, + [0x2db] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2dc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2dd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + .operation = RL78_OPERATION_AND1 }, + [0x2de] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + .operation = RL78_OPERATION_OR1 }, + [0x2df] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x2e1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2e2] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + .operation = RL78_OPERATION_SET1 }, + [0x2e3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2e4] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2e5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + .operation = RL78_OPERATION_AND1 }, + [0x2e6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + .operation = RL78_OPERATION_OR1 }, + [0x2e7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + .operation = RL78_OPERATION_XOR1 }, + [0x2e9] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2ea] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + .operation = RL78_OPERATION_SET1 }, + [0x2eb] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2ec] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2ed] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + .operation = RL78_OPERATION_AND1 }, + [0x2ee] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + .operation = RL78_OPERATION_OR1 }, + [0x2ef] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x280-0x28f + [0x2f1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2f2] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + .operation = RL78_OPERATION_SET1 }, + [0x2f3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2f4] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2f5] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + .operation = RL78_OPERATION_AND1 }, + [0x2f6] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + .operation = RL78_OPERATION_OR1 }, + [0x2f7] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + .operation = RL78_OPERATION_XOR1 }, + [0x2f9] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + .operation = RL78_OPERATION_MOV1 }, + [0x2fa] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + .operation = RL78_OPERATION_SET1 }, + [0x2fb] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + .operation = RL78_OPERATION_CLR1 }, + [0x2fc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + .operation = RL78_OPERATION_MOV1 }, + [0x2fd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + .operation = RL78_OPERATION_AND1 }, + [0x2fe] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + .operation = RL78_OPERATION_OR1 }, + [0x2ff] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_PSW_CY }, + { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + .operation = RL78_OPERATION_XOR1 }, + + // 0x300-0x30f + [0x300] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x301] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x302] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x303] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x304] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x305] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + + // 0x310-0x31f + [0x310] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x311] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x312] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x313] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x314] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x315] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x317] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SHL }, + [0x318] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SHL }, + [0x319] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SHL }, + [0x31a] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SHR }, + [0x31b] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SAR }, + [0x31c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SHLW }, + [0x31d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SHLW }, + [0x31e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SHRW }, + [0x31f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 1 }, + .operation = RL78_OPERATION_SARW }, + + // 0x320-0x32f + [0x320] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x321] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x322] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x323] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x324] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x325] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x327] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SHL }, + [0x328] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SHL }, + [0x329] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SHL }, + [0x32a] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SHR }, + [0x32b] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SAR }, + [0x32c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SHLW }, + [0x32d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SHLW }, + [0x32e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SHRW }, + [0x32f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 2 }, + .operation = RL78_OPERATION_SARW }, + + // 0x330-0x33f + [0x330] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x331] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x332] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x333] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x334] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x335] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x337] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SHL }, + [0x338] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SHL }, + [0x339] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SHL }, + [0x33a] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SHR }, + [0x33b] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SAR }, + [0x33c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SHLW }, + [0x33d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SHLW }, + [0x33e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SHRW }, + [0x33f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 3 }, + .operation = RL78_OPERATION_SARW }, + + // 0x340-0x34f + [0x340] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x341] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x342] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x343] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x344] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x345] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x347] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SHL }, + [0x348] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SHL }, + [0x349] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SHL }, + [0x34a] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SHR }, + [0x34b] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SAR }, + [0x34c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SHLW }, + [0x34d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SHLW }, + [0x34e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SHRW }, + [0x34f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 4 }, + .operation = RL78_OPERATION_SARW }, + + // 0x350-0x35f + [0x350] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x351] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x352] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x353] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x354] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x355] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x357] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SHL }, + [0x358] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SHL }, + [0x359] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SHL }, + [0x35a] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SHR }, + [0x35b] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SAR }, + [0x35c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SHLW }, + [0x35d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SHLW }, + [0x35e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SHRW }, + [0x35f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 5 }, + .operation = RL78_OPERATION_SARW }, + + // 0x360-0x36f + [0x360] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x361] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x362] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x363] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x364] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x365] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x367] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SHL }, + [0x368] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SHL }, + [0x369] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SHL }, + [0x36a] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SHR }, + [0x36b] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SAR }, + [0x36c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SHLW }, + [0x36d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SHLW }, + [0x36e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SHRW }, + [0x36f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 6 }, + .operation = RL78_OPERATION_SARW }, + + // 0x370-0x37f + [0x370] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x371] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x372] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x373] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x374] = { { .type = RL78_OP_TYPE_SADDR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x375] = { { .type = RL78_OP_TYPE_SYMBOL, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_A, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x377] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_C }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SHL }, + [0x378] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_B }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SHL }, + [0x379] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SHL }, + [0x37a] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SHR }, + [0x37b] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_A }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SAR }, + [0x37c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SHLW }, + [0x37d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SHLW }, + [0x37e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SHRW }, + [0x37f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 7 }, + .operation = RL78_OPERATION_SARW }, + + // 0x380-0x38f + [0x380] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x381] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x382] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x383] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x384] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x385] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 0 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x38c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 8 }, + .operation = RL78_OPERATION_SHLW }, + [0x38d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 8 }, + .operation = RL78_OPERATION_SHLW }, + [0x38e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 8 }, + .operation = RL78_OPERATION_SHRW }, + [0x38f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 8 }, + .operation = RL78_OPERATION_SARW }, + + // 0x390-0x39f + [0x390] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x391] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x392] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x393] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x394] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x395] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 1 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x39c] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 9 }, + .operation = RL78_OPERATION_SHLW }, + [0x39d] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 9 }, + .operation = RL78_OPERATION_SHLW }, + [0x39e] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 9 }, + .operation = RL78_OPERATION_SHRW }, + [0x39f] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 9 }, + .operation = RL78_OPERATION_SARW }, + + // 0x3a0-0x3af + [0x3a0] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3a1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3a2] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3a3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3a4] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3a5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 2 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3ac] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 10 }, + .operation = RL78_OPERATION_SHLW }, + [0x3ad] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 10 }, + .operation = RL78_OPERATION_SHLW }, + [0x3ae] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 10 }, + .operation = RL78_OPERATION_SHRW }, + [0x3af] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 10 }, + .operation = RL78_OPERATION_SARW }, + + // 0x3b0-0x3bf + [0x3b0] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3b1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3b2] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3b3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3b4] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3b5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 3 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3bc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 11 }, + .operation = RL78_OPERATION_SHLW }, + [0x3bd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 11 }, + .operation = RL78_OPERATION_SHLW }, + [0x3be] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 11 }, + .operation = RL78_OPERATION_SHRW }, + [0x3bf] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 11 }, + .operation = RL78_OPERATION_SARW }, + + // 0x3c0-0x3cf + [0x3c0] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3c1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3c2] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3c3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3c4] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3c5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 4 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3cc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 12 }, + .operation = RL78_OPERATION_SHLW }, + [0x3cd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 12 }, + .operation = RL78_OPERATION_SHLW }, + [0x3ce] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 12 }, + .operation = RL78_OPERATION_SHRW }, + [0x3cf] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 12 }, + .operation = RL78_OPERATION_SARW }, + + // 0x3d0-0x3df + [0x3d0] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3d1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3d2] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3d3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3d4] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3d5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 5 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3dc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 13 }, + .operation = RL78_OPERATION_SHLW }, + [0x3dd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 13 }, + .operation = RL78_OPERATION_SHLW }, + [0x3de] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 13 }, + .operation = RL78_OPERATION_SHRW }, + [0x3df] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 13 }, + .operation = RL78_OPERATION_SARW }, + + // 0x3e0-0x3ef + [0x3e0] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3e1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3e2] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3e3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3e4] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3e5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 6 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3ec] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 14 }, + .operation = RL78_OPERATION_SHLW }, + [0x3ed] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 14 }, + .operation = RL78_OPERATION_SHLW }, + [0x3ee] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 14 }, + .operation = RL78_OPERATION_SHRW }, + [0x3ef] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 14 }, + .operation = RL78_OPERATION_SARW }, + + // 0x3f0-0x3ff + [0x3f0] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3f1] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BTCLR }, + [0x3f2] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3f3] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BT }, + [0x3f4] = { { .type = RL78_OP_TYPE_SFR, .flags = RL78_OP_FLAG_BA, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3f5] = { { .type = RL78_OP_TYPE_INDIRECT_ADDR, .flags = RL78_OP_FLAG_BA, .v0 = RL78_GPR_HL, .v1 = 7 }, + { .type = RL78_OP_TYPE_RELATIVE_ADDR_8 }, + .operation = RL78_OPERATION_BF }, + [0x3fc] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_BC }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 15 }, + .operation = RL78_OPERATION_SHLW }, + [0x3fd] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 15 }, + .operation = RL78_OPERATION_SHLW }, + [0x3fe] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 15 }, + .operation = RL78_OPERATION_SHRW }, + [0x3ff] = { { .type = RL78_OP_TYPE_SYMBOL, .v0 = RL78_GPR_AX }, + { .type = RL78_OP_TYPE_DECIMAL, .v0 = 15 }, + .operation = RL78_OPERATION_SARW }, +}; diff --git a/librz/asm/arch/rl78/rl78_maps.h b/librz/asm/arch/rl78/rl78_maps.h new file mode 100644 index 00000000000..0d35d5152e9 --- /dev/null +++ b/librz/asm/arch/rl78/rl78_maps.h @@ -0,0 +1,11 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RL78_MAPS_H +#define RL78_MAPS_H + +#include "rl78_instr.h" + +extern RL78Instr rl78_instr_maps[4 * 256]; + +#endif diff --git a/librz/asm/arch/rl78/rl78_operand.c b/librz/asm/arch/rl78/rl78_operand.c new file mode 100644 index 00000000000..53021d9bd32 --- /dev/null +++ b/librz/asm/arch/rl78/rl78_operand.c @@ -0,0 +1,136 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#include "rl78_operand.h" + +#include +#include +#include + +static const char *RL78_STRINGS_SYMBOLS[] = { + [RL78_GPR_X] = "x", + [RL78_GPR_A] = "a", + [RL78_GPR_C] = "c", + [RL78_GPR_B] = "b", + [RL78_GPR_E] = "e", + [RL78_GPR_D] = "d", + [RL78_GPR_L] = "l", + [RL78_GPR_H] = "h", + [RL78_GPR_AX] = "ax", + [RL78_GPR_BC] = "bc", + [RL78_GPR_DE] = "de", + [RL78_GPR_HL] = "hl", + [RL78_SFR_MEM] = "mem", + [RL78_SFR_PMC] = "pmc", + [RL78_SFR_ES] = "es", + [RL78_SFR_CS] = "cs", + [RL78_SFR_PSW] = "psw", + [RL78_SFR_SPH] = "sph", + [RL78_SFR_SPL] = "spl", + [RL78_CR_PC] = "pc", + [RL78_CR_PSW] = "psw", + [RL78_CR_SP] = "sp", + [RL78_RB_RB0] = "rb0", + [RL78_RB_RB1] = "rb1", + [RL78_RB_RB2] = "rb2", + [RL78_RB_RB3] = "rb3", + [RL78_PSW_CY] = "cy", + [RL78_PSW_AC] = "ac", + [RL78_PSW_Z] = "z", +}; + +bool rl78_operand_to_string(RzStrBuf RZ_OUT *dst, const RL78Operand RZ_BORROW *operand) { + if (operand->type <= RL78_OP_TYPE_NONE || + operand->type >= _RL78_OP_TYPE_COUNT) { + return false; + } + + RzStrBuf strbuf; + switch (operand->type) { + case RL78_OP_TYPE_IMMEDIATE_8: + case RL78_OP_TYPE_IMMEDIATE_16: + rz_strf(strbuf.buf, "#0x%" PFMT32x, operand->v0); + break; + case RL78_OP_TYPE_SYMBOL: + rz_return_val_if_fail(rl78_symbol_valid(operand->v0), false); + + rz_strf(strbuf.buf, "%s", RL78_STRINGS_SYMBOLS[operand->v0]); + break; + case RL78_OP_TYPE_SFR: + case RL78_OP_TYPE_SADDR: + if (rl78_symbol_valid(operand->v0)) { + rz_strf(strbuf.buf, "%s", RL78_STRINGS_SYMBOLS[operand->v0]); + } else { + rz_strf(strbuf.buf, "0x%" PFMT32x, operand->v0); + } + break; + case RL78_OP_TYPE_ABSOLUTE_ADDR_16: + if (rl78_symbol_valid(operand->v0)) { + rz_strf(strbuf.buf, "%s", RL78_STRINGS_SYMBOLS[operand->v0]); + } else { + rz_strf(strbuf.buf, "!0x%" PFMT32x, operand->v0); + } + break; + case RL78_OP_TYPE_DECIMAL: + rz_strf(strbuf.buf, "%d", operand->v0); + break; + case RL78_OP_TYPE_ABSOLUTE_ADDR_20: + if (rl78_symbol_valid(operand->v0)) { + rz_strf(strbuf.buf, "%s", RL78_STRINGS_SYMBOLS[operand->v0]); + } else { + rz_strf(strbuf.buf, "!!0x%" PFMT32x, operand->v0); + } + break; + case RL78_OP_TYPE_RELATIVE_ADDR_8: + rz_strf(strbuf.buf, "$0x%" PFMT32x, operand->v0); + break; + case RL78_OP_TYPE_RELATIVE_ADDR_16: + rz_strf(strbuf.buf, "$!0x%" PFMT32x, operand->v0); + break; + case RL78_OP_TYPE_INDIRECT_ADDR: + if (rl78_symbol_valid(operand->v0)) { + rz_strf(strbuf.buf, "[%s]", RL78_STRINGS_SYMBOLS[operand->v0]); + } else { + rz_strf(strbuf.buf, "[0x%" PFMT32x "]", operand->v0); + } + + break; + case RL78_OP_TYPE_BASED_ADDR_8: + rz_return_val_if_fail(rl78_symbol_valid(operand->v0), false); + + rz_strf(strbuf.buf, "[%s+0x%" PFMT32x "]", + RL78_STRINGS_SYMBOLS[operand->v0], operand->v1); + break; + case RL78_OP_TYPE_BASED_ADDR_16: + rz_return_val_if_fail(rl78_symbol_valid(operand->v0), false); + + rz_strf(strbuf.buf, "0x%" PFMT32x "[%s]", + operand->v1, RL78_STRINGS_SYMBOLS[operand->v0]); + break; + case RL78_OP_TYPE_BASED_INDEX_ADDR: + rz_return_val_if_fail(rl78_symbol_valid(operand->v0) && + rl78_symbol_valid(operand->v1), + false); + + rz_strf(strbuf.buf, "[%s+%s]", + RL78_STRINGS_SYMBOLS[operand->v0], + RL78_STRINGS_SYMBOLS[operand->v1]); + break; + default: + rz_warn_if_reached(); + } + + // prefix (extension addressing) and suffix (bit index) + const char *prefix = operand->flags & RL78_OP_FLAG_ES ? "es:" : ""; + if (operand->flags & RL78_OP_FLAG_BA) { + rz_strf(dst->buf, "%s%s.%d", prefix, strbuf.buf, operand->v1); + } else { + rz_strf(dst->buf, "%s%s", prefix, strbuf.buf); + } + + return true; +} + +bool rl78_symbol_valid(int symbol) { + return symbol >= 0 && symbol < _RL78_SYMBOL_COUNT; +} diff --git a/librz/asm/arch/rl78/rl78_operand.h b/librz/asm/arch/rl78/rl78_operand.h new file mode 100644 index 00000000000..a4c5dc25d42 --- /dev/null +++ b/librz/asm/arch/rl78/rl78_operand.h @@ -0,0 +1,107 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RL78_OP_H +#define RL78_OP_H + +#include +#include + +typedef enum RL78Label { + // 8-bit general-purpose registers + RL78_GPR_X, + RL78_GPR_A, + RL78_GPR_C, + RL78_GPR_B, + RL78_GPR_E, + RL78_GPR_D, + RL78_GPR_L, + RL78_GPR_H, + + // 16-bit general-purpose registers + RL78_GPR_AX, + RL78_GPR_BC, + RL78_GPR_DE, + RL78_GPR_HL, + + // special function registers + RL78_SFR_MEM, + RL78_SFR_PMC, // processor mode control + RL78_SFR_ES, // higher part of address for data access + RL78_SFR_CS, // higher part of address for branching + RL78_SFR_PSW, // program status word + RL78_SFR_SPH, + RL78_SFR_SPL, + + // control registers + RL78_CR_PC, // program counter + RL78_CR_PSW, // program status word + RL78_CR_SP, // stack pointer + + // register banks + RL78_RB_RB0, + RL78_RB_RB1, + RL78_RB_RB2, + RL78_RB_RB3, + + // program status word bits and flags + RL78_PSW_CY, // carry + RL78_PSW_AC, // auxiliary carry + RL78_PSW_Z, // zero + + _RL78_SYMBOL_COUNT +} RL78Label; + +typedef enum RL78OperandType { + RL78_OP_TYPE_NONE, // used for instructions with less than 2 operands + RL78_OP_TYPE_IMMEDIATE_8, // #byte + RL78_OP_TYPE_IMMEDIATE_16, // #word + + // operands of type SFR and SADDR will be parsed into + // RL78_OP_TYPE_SYMBOL if they point to a labeled address + RL78_OP_TYPE_SFR, // special function register + RL78_OP_TYPE_SADDR, // short addressing + RL78_OP_TYPE_SYMBOL, // A, X, BC + RL78_OP_TYPE_DECIMAL, // only used for shifts + + RL78_OP_TYPE_ABSOLUTE_ADDR_16, // !... + RL78_OP_TYPE_ABSOLUTE_ADDR_20, // !!... + RL78_OP_TYPE_RELATIVE_ADDR_8, // $... + RL78_OP_TYPE_RELATIVE_ADDR_16, // $!... + RL78_OP_TYPE_INDIRECT_ADDR, // [HL] + RL78_OP_TYPE_BASED_ADDR_8, // [HL+byte] + RL78_OP_TYPE_BASED_ADDR_16, // word[HL] + RL78_OP_TYPE_BASED_INDEX_ADDR, // [HL+C] + + _RL78_OP_TYPE_COUNT +} RL78OperandType; + +typedef enum RL78OperandFlags { + RL78_OP_FLAG_BA = 1 << 0, // bit addressing (bit index stored in v1) + RL78_OP_FLAG_ES = 1 << 1 // extension addressing +} RL78OperandFlags; + +typedef struct RL78Operand { + int v0; // contains label enum if applicable or immediate data + int v1; // contains additional data like the offset for based addressing + int flags; + RL78OperandType type; +} RL78Operand; + +/** + * \brief Convert an RL78 operand to a string + * \param dst A caller-supplied character buffer to print into + * \param n Size of dst + * \param operand RL78 operand to be printed + * \return false If operand->type is out of range or equal to RL78_OP_TYPE_NONE + */ +bool rl78_operand_to_string(RzStrBuf RZ_OUT *dst, const RL78Operand RZ_BORROW *operand); + +/** + * \brief Check whether a symbol is valid, i.e. is in enum bounds + * \param symbol A symbol + * \return false If symbol is out of range (i.e. < 0 or >= _RL78_SYMBOL_COUNT) + */ +bool rl78_symbol_valid(int symbol); + +#endif diff --git a/librz/asm/d/rl78.sdb.txt b/librz/asm/d/rl78.sdb.txt new file mode 100644 index 00000000000..eca1b8628f3 --- /dev/null +++ b/librz/asm/d/rl78.sdb.txt @@ -0,0 +1,76 @@ +add=byte data addition +addc=addition of byte data with carry +addw=word data addition +addw=addition of stack pointer +and=logical product of byte data +and1=1 bit data logical product +bc=conditional branch with carry flag (cy = 1) +bf=conditional branch by bit test (byte data bit = 0) +bh=conditional branch by numeric value comparison ((z | cy) = 0) +bnc=conditional branch with carry flag (cy = 0) +bnh=conditional branch by numeric value comparison ((z | cy) = 1) +bnz=conditional branch with zero flag (z = 0) +br=unconditional branch +brk=software vectored interrupt +bt=conditional branch by bit test (byte data bit = 1) +btclr=conditional branch and clear by bit test (byte data bit =1) +bz=conditional branch with zero flag (z = 1) +call=subroutine call +callt=subroutine call (refer to the call table) +clrb=byte data clear +clrw=word data clear +clr1=1 bit data clear +cmp=byte data comparison +cmps=byte data comparison +cmpw=word data comparison +cmp0=byte data zero comparison +dec=byte data decrement +decw=word data decrement +di=interrupt disabled +divhu=unsigned division of data +divwu=unsigned division of data +ei=interrupt enabled +halt=halt mode set +inc=byte data increment +incw=word data increment +mach=signed multiplication and accumulation of data +machu=unsigned multiplication and accumulation of data +mov=byte data transfer +movs=byte data transfer and psw change +movw=word data transfer +movw=rp, sp word data transfer with stack pointer +movw=sp, src word data transfer with stack pointer +mov1=1 bit data transfer +mulh=signed multiplication of data +mulhu=unsigned multiplication of data +mulu=unsigned multiplication of data +nop=no operation +not1=1 bit data logical negation +oneb=byte data 01h set +onew=word data 0001h set +or=logical sum of byte data +or1=1 bit data logical sum +pop=pop +push=push +ret=return from subroutine +retb=return from software vectored interrupt +reti=return from hardware vectored interrupt +rol=byte data rotation to the left +rolc=byte data rotation to the left with carry +rolwc=word data rotation to the left with carry +ror=byte data rotation to the right +rorc=byte data rotation to the right with carry +sar=arithmetic shift to the right +sarw=arithmetic shift to the right +sel=rbn register bank selection +set1=1 bit data set +shl=logical shift to the left +shlw=logical shift to the left +shr=logical shift to the right +shrw=logical shift to the right +skc=skip with carry flag (cy = 1) +skh=skip with numeric value comparison ((z | cy) = 0) +sknc=skip with carry flag (cy = 0) +sknh=skip with numeric value comparison ((z | cy) = 1) +sknz=skip with zero flag (z = 0) +skz=skip with zero flag (z = 1) diff --git a/librz/asm/meson.build b/librz/asm/meson.build index d8f4da52b81..fb929dec55c 100644 --- a/librz/asm/meson.build +++ b/librz/asm/meson.build @@ -35,6 +35,7 @@ asm_plugins_list = [ 'ppc_cs', 'propeller', 'pyc', + 'rl78', 'rsp', 'sh', 'snes', @@ -122,6 +123,7 @@ rz_asm_sources = [ 'p/asm_ppc_cs.c', 'p/asm_propeller.c', 'p/asm_pyc.c', + 'p/asm_rl78.c', 'p/asm_rsp.c', 'p/asm_sh.c', 'p/asm_snes.c', @@ -214,6 +216,10 @@ rz_asm_sources = [ 'arch/pyc/opcode_arg_fmt.c', 'arch/pyc/opcode.c', 'arch/pyc/pyc_dis.c', + 'arch/rl78/rl78_instr.c', + 'arch/rl78/rl78_maps.c', + 'arch/rl78/rl78_operand.c', + 'arch/rl78/rl78.c', 'arch/rsp/rsp_idec.c', 'arch/sh/disassembler.c', 'arch/sh/assembler.c', diff --git a/librz/asm/p/asm_rl78.c b/librz/asm/p/asm_rl78.c new file mode 100644 index 00000000000..9344082adea --- /dev/null +++ b/librz/asm/p/asm_rl78.c @@ -0,0 +1,54 @@ +// SPDX-FileCopyrightText: 2023 Bastian Engel +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include +#include + +#include "../arch/rl78/rl78.h" + +static int assemble(RzAsm *a, RzAsmOp *op, const char *buf) { + return 0x69; +} + +static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { + RL78Instr instr = { 0 }; + size_t bytes_read = 0; + if (!rl78_dis(&instr, &bytes_read, buf, len)) { + rz_strbuf_set(&op->buf_asm, "(invalid)"); + return bytes_read; + } + + RzStrBuf *instr_strbuf = rz_strbuf_new(""); + if (rl78_instr_to_string(instr_strbuf, &instr)) { + rz_strbuf_copy(&op->buf_asm, instr_strbuf); + } else { + rz_strbuf_set(&op->buf_asm, "(invalid)"); + } + + rz_strbuf_free(instr_strbuf); + + op->size = bytes_read; + return bytes_read; +} + +RzAsmPlugin rz_asm_plugin_rl78 = { + .name = "rl78", + .arch = "rl78", + .desc = "Renesas RL78 disassembler", + .author = "Bastian Engel", + .license = "LGPL3", + .bits = 32, + .endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG, + .assemble = &assemble, + .disassemble = &disassemble +}; + +#ifndef RZ_PLUGIN_INCORE +RZ_API RzLibStruct rizin_plugin = { + .type = RZ_LIB_TYPE_ASM, + .data = &rz_asm_plugin_rl78, + .version = RZ_VERSION +}; +#endif diff --git a/librz/include/rz_analysis.h b/librz/include/rz_analysis.h index 66236344f05..d24adeaf745 100644 --- a/librz/include/rz_analysis.h +++ b/librz/include/rz_analysis.h @@ -2406,6 +2406,7 @@ extern RzAnalysisPlugin rz_analysis_plugin_ppc_cs; extern RzAnalysisPlugin rz_analysis_plugin_propeller; extern RzAnalysisPlugin rz_analysis_plugin_riscv; extern RzAnalysisPlugin rz_analysis_plugin_riscv_cs; +extern RzAnalysisPlugin rz_analysis_plugin_rl78; extern RzAnalysisPlugin rz_analysis_plugin_rsp; extern RzAnalysisPlugin rz_analysis_plugin_sh; extern RzAnalysisPlugin rz_analysis_plugin_snes; diff --git a/librz/include/rz_asm.h b/librz/include/rz_asm.h index a8c3de949cc..39b6707d08e 100644 --- a/librz/include/rz_asm.h +++ b/librz/include/rz_asm.h @@ -258,6 +258,7 @@ extern RzAsmPlugin rz_asm_plugin_ppc_cs; extern RzAsmPlugin rz_asm_plugin_propeller; extern RzAsmPlugin rz_asm_plugin_riscv; extern RzAsmPlugin rz_asm_plugin_riscv_cs; +extern RzAsmPlugin rz_asm_plugin_rl78; extern RzAsmPlugin rz_asm_plugin_rsp; extern RzAsmPlugin rz_asm_plugin_sh; extern RzAsmPlugin rz_asm_plugin_snes; diff --git a/test/db/analysis/rl78 b/test/db/analysis/rl78 new file mode 100644 index 00000000000..e6e250b420e --- /dev/null +++ b/test/db/analysis/rl78 @@ -0,0 +1,205 @@ +NAME=RL78 caesar_nostrip info +FILE=bins/rl78/caesar_nostrip +ARGS=-a rl78 +CMDS=< 0x0000055f br $0x0 + ;-- _make_uppercase: +/ void make_uppercase(char *buf, size_t n) +| ; arg char *buf @ ... +| ; arg size_t n @ ... +| 0x000005a3 subw sp, #0x18 ; caesar.c:24 ; void make_uppercase(char *buf, size_t n) +| 0x000005a5 movw [sp+0x0], ax +| 0x000005a7 movw ax, bc +| 0x000005a8 movw [sp+0x2], ax +| 0x000005aa clrw ax +| 0x000005ab movw [sp+0x4], ax ; caesar.c:25 +\ @-> 0x000005ad br $0x0 + ; CALL XREFS from sym._main @ +0x8f, +0x9d + ;-- _hash: +/ int hash(const char *buf, size_t n) +| ; arg const char *buf @ ... +| ; arg size_t n @ ... +| ; var int sum @ ... +| 0x00000634 subw sp, #0x1e ; caesar.c:33 ; int hash(const char *buf, size_t n) +| 0x00000636 movw [sp+0x4], ax +| 0x00000638 movw ax, bc +| 0x00000639 movw [sp+0x6], ax +| 0x0000063b clrw ax +| 0x0000063c movw [sp+0xc], ax ; caesar.c:34 +| 0x0000063e movw [sp+0x8], ax +| 0x00000640 movw ax, [sp+0xc] ; caesar.c:35 +| 0x00000642 movw [sp+0xa], ax +\ @-> 0x00000644 br $0x0 + ; CALL XREF from entry0 @ 0x7f8 + ;-- _main: +/ int main(int argc, char **argv) +| ; arg int argc @ ... +| ; arg char **argv @ ... +| ; var const struct operations ops @ ... +| ; var size_t len @ ... +| ; var char *decrypted @ ... +| ; var char *uppercase @ ... +| ; var const char *pw @ ... +| ; var size_t pwlen @ ... +| 0x000006b3 subw sp, #0x26 ; caesar.c:43 ; int main(int argc, char **argv) +| 0x000006b5 movw de, #0x0 +| 0x000006b8 movw [sp+0x14], ax +| 0x000006ba movw ax, de +| 0x000006bb movw [sp+0x0], ax +| 0x000006bd movw ax, [sp+0x14] +| 0x000006bf movw [sp+0x2], ax +| 0x000006c1 movw ax, bc +| 0x000006c2 movw [sp+0x4], ax +| 0x000006c4 movw ax, !0x3004 ; caesar.c:44 +| 0x000006c7 movw [sp+0x8], ax +| 0x000006c9 movw ax, !0x3002 +| 0x000006cc movw [sp+0x6], ax +| 0x000006ce movw ax, !0x5700 ; caesar.c:49 +| 0x000006d1 call !0x84e ; sym._strlen ; size_t strlen(const char *s) +| 0x000006d4 movw [sp+0xa], ax +| 0x000006d6 movw ax, [sp+0xa] ; caesar.c:50 +| 0x000006d8 cmpw ax, #0x41 +| ,=< 0x000006db bc $0x8 +| @=-> 0x000006dd br $0x0 +.. +| |`-> 0x000006e3 dec c +| | 0x000006e4 nop +| | 0x000006e5 movw ax, [sp+0xa] ; caesar.c:54 +| | 0x000006e7 call !0xb18 ; sym._malloc ; void *malloc(size_t size) +| | 0x000006ea movw [sp+0xc], ax +| | 0x000006ec movw ax, [sp+0x6] ; caesar.c:55 +| | 0x000006ee movw [sp+0x16], ax +| | 0x000006f0 movw ax, [sp+0xc] +| | 0x000006f2 movw bc, !0x5700 +| | 0x000006f5 movw [sp+0x18], ax +| | 0x000006f7 movw ax, [sp+0xa] +| | 0x000006f9 movw de, ax +| | 0x000006fa movw ax, [sp+0x18] +| | 0x000006fc xchw ax, hl +| | 0x000006fd movw ax, [sp+0x16] +| | 0x000006ff xchw ax, hl +| | 0x00000700 call hl +| | 0x00000702 cmpw ax, #0x0 +| |,=< 0x00000705 bnz $0xc +| @==-> 0x00000707 br $0x0 +.. +| ,=`-> 0x00000711 br $0x64 +.. +| || @ ; CODE XREF from dbg.main @ 0x711 +| || @ ; CODE XREF from sym._main @ +0xb3 +\ ``-@-> 0x00000775 br $0x0 +EOF +RUN + +NAME=RL78 caesar_nostrip function list +FILE=bins/rl78/caesar_nostrip +ARGS=-a rl78 +CMDS=< 464 entry0 +0x0000093a 8 81 -> 83 sym.___do_fini +0x000008de 2 11 sym.___do_init +0x000013d7 7 90 -> 91 sym._malloc_extend_top +0x00000552 2 15 dbg.decrypt +0x00000b1f 1 7 sym._free +0x00000634 2 18 dbg.hash +0x000006b3 6 196 -> 86 dbg.main +0x000005a3 2 12 dbg.make_uppercase +0x00000b18 1 7 sym._malloc +0x000015fb 1 7 sym._strdup +0x0000084e 2 11 sym._strlen +0x00000e5e 1 20 sym.__malloc_r +0x0000083e 1 8 sym._memcpy +0x000009ab 3 26 sym._exit +0x000009c5 1 24 sym.___call_exitprocs +0x00000b16 8 345 -> 80 sym.__exit +0x00000816 7 39 sym._rl78_run_fini_array +0x0000080b 1 11 sym._rl78_run_init_array +0x00000800 1 11 sym._rl78_run_preinit_array +0x000015e1 3 26 -> 28 sym._sbrk +0x00000b26 1 11 sym.__free_r +0x00000d9e 3 49 sym.__malloc_trim_r +0x000015bd 1 1 sym.___malloc_lock +0x000015be 1 1 sym.___malloc_unlock +0x000015bf 4 34 sym.__sbrk_r +0x00001602 3 44 sym.__strdup_r +0x00000896 1 8 loc.__COM_slrem +0x0000162e 1 13 loc.__rl78_init +0x0000086e 5 25 loc.__COM_lshl +EOF +RUN diff --git a/test/db/asm/rl78 b/test/db/asm/rl78 new file mode 100644 index 00000000000..74d6f3ec6a4 --- /dev/null +++ b/test/db/asm/rl78 @@ -0,0 +1,1331 @@ +d "mov x, #0x30" 5030 +d "mov a, #0x30" 5130 +d "mov c, #0x30" 5230 +d "mov b, #0x30" 5330 +d "mov e, #0x30" 5430 +d "mov d, #0x30" 5530 +d "mov l, #0x30" 5630 +d "mov h, #0x30" 5730 +d "mov 0xffe46, #0x30" cd2630 +d "mov pmc, #0x30" cefe30 +d "mov !0x30a4, #0x70" cfa43070 +d "mov a, x" 60 +d "mov a, c" 62 +d "mov a, b" 63 +d "mov a, e" 64 +d "mov a, d" 65 +d "mov a, l" 66 +d "mov a, h" 67 +d "mov x, a" 70 +d "mov c, a" 72 +d "mov b, a" 73 +d "mov e, a" 74 +d "mov d, a" 75 +d "mov l, a" 76 +d "mov h, a" 77 +d "mov a, 0xffe46" 8d26 +d "mov 0xffe46, a" 9d26 +d "mov a, pmc" 8efe +d "mov pmc, a" 9efe +d "mov a, !0x30a4" 8fa430 +d "mov !0x30a4, a" 9fa430 +d "mov psw, #0x30" cefa30 +d "mov a, psw" 8efa +d "mov psw, a" 9efa +d "mov es, #0x30" 4130 +d "mov es, 0xffe46" 61b826 +d "mov a, es" 8efd +d "mov es, a" 9efd +d "mov cs, #0x30" cefc30 +d "mov a, cs" 8efc +d "mov cs, a" 9efc +d "mov a, [de]" 89 +d "mov [de], a" 99 +d "mov [de+0x30], #0x17" ca3017 +d "mov a, [de+0x30]" 8a30 +d "mov [de+0x30], a" 9a30 +d "mov a, [hl]" 8b +d "mov [hl], a" 9b +d "mov [hl+0x30], #0x17" cc3017 +d "mov a, [hl+0x30]" 8c30 +d "mov [hl+0x30], a" 9c30 +d "mov a, [hl+b]" 61c9 +d "mov [hl+b], a" 61d9 +d "mov a, [hl+c]" 61e9 +d "mov [hl+c], a" 61f9 +d "mov 0xfa20[b], #0x30" 1920fa30 +d "mov a, 0xfa20[b]" 0920fa +d "mov 0xfa20[b], a" 1820fa +d "mov 0xfa20[c], #0x30" 3820fa30 +d "mov a, 0xfa20[c]" 2920fa +d "mov 0xfa20[c], a" 2820fa +d "mov 0xfa20[bc], #0x30" 3920fa30 +d "mov a, 0xfa20[bc]" 4920fa +d "mov 0xfa20[bc], a" 4820fa +d "mov [sp+0x30], #0x17" c83017 +d "mov a, [sp+0x30]" 8830 +d "mov [sp+0x30], a" 9830 +d "mov b, 0xffe46" e826 +d "mov b, !0x30a4" e9a430 +d "mov c, 0xffe46" f826 +d "mov c, !0x30a4" f9a430 +d "mov x, 0xffe46" d826 +d "mov x, !0x30a4" d9a430 +d "mov es:!0x30a4, #0x17" 11cfa43017 +d "mov a, es:!0x30a4" 118fa430 +d "mov es:!0x30a4, a" 119fa430 +d "mov a, es:[de]" 1189 +d "mov es:[de], a" 1199 +d "mov es:[de+0x30], #0x17" 11ca3017 +d "mov a, es:[de+0x30]" 118a30 +d "mov es:[de+0x30], a" 119a30 +d "mov a, es:[hl]" 118b +d "mov es:[hl], a" 119b +d "mov es:[hl+0x30], #0x17" 11cc3017 +d "mov a, es:[hl+0x30]" 118c30 +d "mov es:[hl+0x30], a" 119c30 +d "mov a, es:[hl+b]" 1161c9 +d "mov es:[hl+b], a" 1161d9 +d "mov a, es:[hl+c]" 1161e9 +d "mov es:[hl+c], a" 1161f9 +d "mov es:0xfa20[b], #0x30" 111920fa30 +d "mov a, es:0xfa20[b]" 110920fa +d "mov es:0xfa20[b], a" 111820fa +d "mov es:0xfa20[c], #0x30" 113820fa30 +d "mov a, es:0xfa20[c]" 112920fa +d "mov es:0xfa20[c], a" 112820fa +d "mov es:0xfa20[bc], #0x30" 113920fa30 +d "mov a, es:0xfa20[bc]" 114920fa +d "mov es:0xfa20[bc], a" 114820fa +d "mov b, es:!0x30a4" 11e9a430 +d "mov c, es:!0x30a4" 11f9a430 +d "mov x, es:!0x30a4" 11d9a430 +d "xch a, x" 08 +d "xch a, c" 618a +d "xch a, b" 618b +d "xch a, e" 618c +d "xch a, d" 618d +d "xch a, l" 618e +d "xch a, h" 618f +d "xch a, 0xffe46" 61a826 +d "xch a, pmc" 61abfe +d "xch a, !0x30a4" 61aaa430 +d "xch a, [de]" 61ae +d "xch a, [de+0x30]" 61af30 +d "xch a, [hl]" 61ac +d "xch a, [hl+0x30]" 61ad30 +d "xch a, [hl+b]" 61b9 +d "xch a, [hl+c]" 61a9 +d "xch a, es:!0x30a4" 1161aaa430 +d "xch a, es:[de]" 1161ae +d "xch a, es:[de+0x30]" 1161af30 +d "xch a, es:[hl]" 1161ac +d "xch a, es:[hl+0x30]" 1161ad30 +d "xch a, es:[hl+b]" 1161b9 +d "xch a, es:[hl+c]" 1161a9 +d "oneb a" e1 +d "oneb x" e0 +d "oneb b" e3 +d "oneb c" e2 +d "oneb 0xffe46" e426 +d "oneb !0x30a4" e5a430 +d "oneb es:!0x30a4" 11e5a430 +d "clrb a" f1 +d "clrb x" f0 +d "clrb b" f3 +d "clrb c" f2 +d "clrb 0xffe46" f426 +d "clrb !0x30a4" f5a430 +d "clrb es:!0x30a4" 11f5a430 +d "movs [hl+0x30], x" 61ce30 +d "movs es:[hl+0x30], x" 1161ce30 +d "movw ax, #0x1337" 303713 +d "movw bc, #0x1337" 323713 +d "movw de, #0x1337" 343713 +d "movw hl, #0x1337" 363713 +d "movw 0xffe46, #0x1337" c9263713 +d "movw pmc, #0x1337" cbfe3713 +d "movw ax, 0xffe46" ad26 +d "movw 0xffe46, ax" bd26 +d "movw ax, pmc" aefe +d "movw pmc, ax" befe +d "movw ax, bc" 13 +d "movw ax, de" 15 +d "movw ax, hl" 17 +d "movw bc, ax" 12 +d "movw de, ax" 14 +d "movw hl, ax" 16 +d "movw ax, !0x30a4" afa430 +d "movw !0x30a4, ax" bfa430 +d "movw ax, [de]" a9 +d "movw [de], ax" b9 +d "movw ax, [de+0x30]" aa30 +d "movw [de+0x30], ax" ba30 +d "movw ax, [hl]" ab +d "movw [hl], ax" bb +d "movw ax, [hl+0x30]" ac30 +d "movw [hl+0x30], ax" bc30 +d "movw ax, 0xfa20[b]" 5920fa +d "movw 0xfa20[b], ax" 5820fa +d "movw ax, 0xfa20[c]" 6920fa +d "movw 0xfa20[c], ax" 6820fa +d "movw ax, 0xfa20[bc]" 7920fa +d "movw 0xfa20[bc], ax" 7820fa +d "movw ax, [sp+0x30]" a830 +d "movw [sp+0x30], ax" b830 +d "movw bc, 0xffe46" da26 +d "movw bc, !0x30a4" dba430 +d "movw de, 0xffe46" ea26 +d "movw de, !0x30a4" eba430 +d "movw hl, 0xffe46" fa26 +d "movw hl, !0x30a4" fba430 +d "movw ax, es:!0x30a4" 11afa430 +d "movw es:!0x30a4, ax" 11bfa430 +d "movw ax, es:[de]" 11a9 +d "movw es:[de], ax" 11b9 +d "movw ax, es:[de+0x30]" 11aa30 +d "movw es:[de+0x30], ax" 11ba30 +d "movw ax, es:[hl]" 11ab +d "movw es:[hl], ax" 11bb +d "movw ax, es:[hl+0x30]" 11ac30 +d "movw es:[hl+0x30], ax" 11bc30 +d "movw ax, es:0xfa20[b]" 115920fa +d "movw es:0xfa20[b], ax" 115820fa +d "movw ax, es:0xfa20[c]" 116920fa +d "movw es:0xfa20[c], ax" 116820fa +d "movw ax, es:0xfa20[bc]" 117920fa +d "movw es:0xfa20[bc], ax" 117820fa +d "movw bc, es:!0x30a4" 11dba430 +d "movw de, es:!0x30a4" 11eba430 +d "movw hl, es:!0x30a4" 11fba430 +d "xchw ax, bc" 33 +d "xchw ax, de" 35 +d "xchw ax, hl" 37 +d "onew ax" e6 +d "onew bc" e7 +d "clrw ax" f6 +d "clrw bc" f7 +d "add a, #0x30" 0c30 +d "add 0xffe46, #0x30" 0a2630 +d "add a, x" 6108 +d "add a, c" 610a +d "add a, b" 610b +d "add a, e" 610c +d "add a, d" 610d +d "add a, l" 610e +d "add a, h" 610f +d "add x, a" 6100 +d "add a, a" 6101 +d "add c, a" 6102 +d "add b, a" 6103 +d "add e, a" 6104 +d "add d, a" 6105 +d "add l, a" 6106 +d "add h, a" 6107 +d "add a, 0xffe46" 0b26 +d "add a, !0x30a4" 0fa430 +d "add a, [hl]" 0d +d "add a, [hl+0x30]" 0e30 +d "add a, [hl+b]" 6180 +d "add a, [hl+c]" 6182 +d "add a, es:!0x30a4" 110fa430 +d "add a, es:[hl]" 110d +d "add a, es:[hl+0x30]" 110e30 +d "add a, es:[hl+b]" 116180 +d "add a, es:[hl+c]" 116182 +d "addc a, #0x30" 1c30 +d "addc 0xffe46, #0x30" 1a2630 +d "addc a, x" 6118 +d "addc a, c" 611a +d "addc a, b" 611b +d "addc a, e" 611c +d "addc a, d" 611d +d "addc a, l" 611e +d "addc a, h" 611f +d "addc x, a" 6110 +d "addc a, a" 6111 +d "addc c, a" 6112 +d "addc b, a" 6113 +d "addc e, a" 6114 +d "addc d, a" 6115 +d "addc l, a" 6116 +d "addc h, a" 6117 +d "addc a, 0xffe46" 1b26 +d "addc a, !0x30a4" 1fa430 +d "addc a, [hl]" 1d +d "addc a, [hl+0x30]" 1e30 +d "addc a, [hl+b]" 6190 +d "addc a, [hl+c]" 6192 +d "addc a, es:!0x30a4" 111fa430 +d "addc a, es:[hl]" 111d +d "addc a, es:[hl+0x30]" 111e30 +d "addc a, es:[hl+b]" 116190 +d "addc a, es:[hl+c]" 116192 +d "sub a, #0x30" 2c30 +d "sub 0xffe46, #0x30" 2a2630 +d "sub a, x" 6128 +d "sub a, c" 612a +d "sub a, b" 612b +d "sub a, e" 612c +d "sub a, d" 612d +d "sub a, l" 612e +d "sub a, h" 612f +d "sub x, a" 6120 +d "sub a, a" 6121 +d "sub c, a" 6122 +d "sub b, a" 6123 +d "sub e, a" 6124 +d "sub d, a" 6125 +d "sub l, a" 6126 +d "sub h, a" 6127 +d "sub a, 0xffe46" 2b26 +d "sub a, !0x30a4" 2fa430 +d "sub a, [hl]" 2d +d "sub a, [hl+0x30]" 2e30 +d "sub a, [hl+b]" 61a0 +d "sub a, [hl+c]" 61a2 +d "sub a, es:!0x30a4" 112fa430 +d "sub a, es:[hl]" 112d +d "sub a, es:[hl+0x30]" 112e30 +d "sub a, es:[hl+b]" 1161a0 +d "sub a, es:[hl+c]" 1161a2 +d "subc a, #0x30" 3c30 +d "subc 0xffe46, #0x30" 3a2630 +d "subc a, x" 6138 +d "subc a, c" 613a +d "subc a, b" 613b +d "subc a, e" 613c +d "subc a, d" 613d +d "subc a, l" 613e +d "subc a, h" 613f +d "subc x, a" 6130 +d "subc a, a" 6131 +d "subc c, a" 6132 +d "subc b, a" 6133 +d "subc e, a" 6134 +d "subc d, a" 6135 +d "subc l, a" 6136 +d "subc h, a" 6137 +d "subc a, 0xffe46" 3b26 +d "subc a, !0x30a4" 3fa430 +d "subc a, [hl]" 3d +d "subc a, [hl+0x30]" 3e30 +d "subc a, [hl+b]" 61b0 +d "subc a, [hl+c]" 61b2 +d "subc a, es:!0x30a4" 113fa430 +d "subc a, es:[hl]" 113d +d "subc a, es:[hl+0x30]" 113e30 +d "subc a, es:[hl+b]" 1161b0 +d "subc a, es:[hl+c]" 1161b2 +d "and a, #0x30" 5c30 +d "and 0xffe46, #0x30" 5a2630 +d "and a, x" 6158 +d "and a, c" 615a +d "and a, b" 615b +d "and a, e" 615c +d "and a, d" 615d +d "and a, l" 615e +d "and a, h" 615f +d "and x, a" 6150 +d "and a, a" 6151 +d "and c, a" 6152 +d "and b, a" 6153 +d "and e, a" 6154 +d "and d, a" 6155 +d "and l, a" 6156 +d "and h, a" 6157 +d "and a, 0xffe46" 5b26 +d "and a, !0x30a4" 5fa430 +d "and a, [hl]" 5d +d "and a, [hl+0x30]" 5e30 +d "and a, [hl+b]" 61d0 +d "and a, [hl+c]" 61d2 +d "and a, es:!0x30a4" 115fa430 +d "and a, es:[hl]" 115d +d "and a, es:[hl+0x30]" 115e30 +d "and a, es:[hl+b]" 1161d0 +d "and a, es:[hl+c]" 1161d2 +d "or a, #0x30" 6c30 +d "or 0xffe46, #0x30" 6a2630 +d "or a, x" 6168 +d "or a, c" 616a +d "or a, b" 616b +d "or a, e" 616c +d "or a, d" 616d +d "or a, l" 616e +d "or a, h" 616f +d "or x, a" 6160 +d "or a, a" 6161 +d "or c, a" 6162 +d "or b, a" 6163 +d "or e, a" 6164 +d "or d, a" 6165 +d "or l, a" 6166 +d "or h, a" 6167 +d "or a, 0xffe46" 6b26 +d "or a, !0x30a4" 6fa430 +d "or a, [hl]" 6d +d "or a, [hl+0x30]" 6e30 +d "or a, [hl+b]" 61e0 +d "or a, [hl+c]" 61e2 +d "or a, es:!0x30a4" 116fa430 +d "or a, es:[hl]" 116d +d "or a, es:[hl+0x30]" 116e30 +d "or a, es:[hl+b]" 1161e0 +d "or a, es:[hl+c]" 1161e2 +d "xor a, #0x30" 7c30 +d "xor 0xffe46, #0x30" 7a2630 +d "xor a, x" 6178 +d "xor a, c" 617a +d "xor a, b" 617b +d "xor a, e" 617c +d "xor a, d" 617d +d "xor a, l" 617e +d "xor a, h" 617f +d "xor x, a" 6170 +d "xor a, a" 6171 +d "xor c, a" 6172 +d "xor b, a" 6173 +d "xor e, a" 6174 +d "xor d, a" 6175 +d "xor l, a" 6176 +d "xor h, a" 6177 +d "xor a, 0xffe46" 7b26 +d "xor a, !0x30a4" 7fa430 +d "xor a, [hl]" 7d +d "xor a, [hl+0x30]" 7e30 +d "xor a, [hl+b]" 61f0 +d "xor a, [hl+c]" 61f2 +d "xor a, es:!0x30a4" 117fa430 +d "xor a, es:[hl]" 117d +d "xor a, es:[hl+0x30]" 117e30 +d "xor a, es:[hl+b]" 1161f0 +d "xor a, es:[hl+c]" 1161f2 +d "cmp a, #0x30" 4c30 +d "cmp 0xffe46, #0x30" 4a2630 +d "cmp a, x" 6148 +d "cmp a, c" 614a +d "cmp a, b" 614b +d "cmp a, e" 614c +d "cmp a, d" 614d +d "cmp a, l" 614e +d "cmp a, h" 614f +d "cmp x, a" 6140 +d "cmp a, a" 6141 +d "cmp c, a" 6142 +d "cmp b, a" 6143 +d "cmp e, a" 6144 +d "cmp d, a" 6145 +d "cmp l, a" 6146 +d "cmp h, a" 6147 +d "cmp a, 0xffe46" 4b26 +d "cmp a, !0x30a4" 4fa430 +d "cmp a, [hl]" 4d +d "cmp a, [hl+0x30]" 4e30 +d "cmp a, [hl+b]" 61c0 +d "cmp a, [hl+c]" 61c2 +d "cmp !0x30a4, #0x17" 40a43017 +d "cmp a, es:!0x30a4" 114fa430 +d "cmp a, es:[hl]" 114d +d "cmp a, es:[hl+0x30]" 114e30 +d "cmp a, es:[hl+b]" 1161c0 +d "cmp a, es:[hl+c]" 1161c2 +d "cmp es:!0x30a4, #0x17" 1140a43017 +d "cmp0 a" d1 +d "cmp0 x" d0 +d "cmp0 b" d3 +d "cmp0 c" d2 +d "cmp0 0xffe46" d426 +d "cmp0 !0x30a4" d5a430 +d "cmp0 es:!0x30a4" 11d5a430 +d "cmps x, [hl+0x30]" 61de30 +d "cmps x, es:[hl+0x30]" 1161de30 +d "addw ax, #0x1337" 043713 +d "addw ax, ax" 01 +d "addw ax, bc" 03 +d "addw ax, de" 05 +d "addw ax, hl" 07 +d "addw ax, 0xffe46" 0626 +d "addw ax, !0x30a4" 02a430 +d "addw ax, [hl+0x30]" 610930 +d "addw ax, es:!0x30a4" 1102a430 +d "addw ax, es:[hl+0x30]" 11610930 +d "subw ax, #0x1337" 243713 +d "subw ax, bc" 23 +d "subw ax, de" 25 +d "subw ax, hl" 27 +d "subw ax, 0xffe46" 2626 +d "subw ax, !0x30a4" 22a430 +d "subw ax, [hl+0x30]" 612930 +d "subw ax, es:!0x30a4" 1122a430 +d "subw ax, es:[hl+0x30]" 11612930 +d "cmpw ax, #0x1337" 443713 +d "cmpw ax, bc" 43 +d "cmpw ax, de" 45 +d "cmpw ax, hl" 47 +d "cmpw ax, 0xffe46" 4626 +d "cmpw ax, !0x30a4" 42a430 +d "cmpw ax, [hl+0x30]" 614930 +d "cmpw ax, es:!0x30a4" 1142a430 +d "cmpw ax, es:[hl+0x30]" 11614930 +d "mulu x" d6 +d "mulhu" cefb01 +d "mulh" cefb02 +d "divhu" cefb03 +d "divwu" cefb0b +d "machu" cefb05 +d "mach" cefb06 +d "inc x" 80 +d "inc a" 81 +d "inc c" 82 +d "inc b" 83 +d "inc e" 84 +d "inc d" 85 +d "inc l" 86 +d "inc h" 87 +d "inc 0xffe46" a426 +d "inc !0x30a4" a0a430 +d "inc [hl+0x30]" 615930 +d "inc es:!0x30a4" 11a0a430 +d "inc es:[hl+0x30]" 11615930 +d "dec x" 90 +d "dec a" 91 +d "dec c" 92 +d "dec b" 93 +d "dec e" 94 +d "dec d" 95 +d "dec l" 96 +d "dec h" 97 +d "dec 0xffe46" b426 +d "dec !0x30a4" b0a430 +d "dec [hl+0x30]" 616930 +d "dec es:!0x30a4" 11b0a430 +d "dec es:[hl+0x30]" 11616930 +d "incw ax" a1 +d "incw bc" a3 +d "incw de" a5 +d "incw hl" a7 +d "incw 0xffe46" a626 +d "incw !0x30a4" a2a430 +d "incw [hl+0x30]" 617930 +d "incw es:!0x30a4" 11a2a430 +d "incw es:[hl+0x30]" 11617930 +d "decw ax" b1 +d "decw bc" b3 +d "decw de" b5 +d "decw hl" b7 +d "decw 0xffe46" b626 +d "decw !0x30a4" b2a430 +d "decw [hl+0x30]" 618930 +d "decw es:!0x30a4" 11b2a430 +d "decw es:[hl+0x30]" 11618930 +d "shr a, 1" 311a +d "shr a, 2" 312a +d "shr a, 3" 313a +d "shr a, 4" 314a +d "shr a, 5" 315a +d "shr a, 6" 316a +d "shr a, 7" 317a +d "shrw ax, 1" 311e +d "shrw ax, 2" 312e +d "shrw ax, 3" 313e +d "shrw ax, 4" 314e +d "shrw ax, 5" 315e +d "shrw ax, 6" 316e +d "shrw ax, 7" 317e +d "shrw ax, 8" 318e +d "shrw ax, 9" 319e +d "shrw ax, 10" 31ae +d "shrw ax, 11" 31be +d "shrw ax, 12" 31ce +d "shrw ax, 13" 31de +d "shrw ax, 14" 31ee +d "shrw ax, 15" 31fe +d "shl a, 1" 3119 +d "shl a, 2" 3129 +d "shl a, 3" 3139 +d "shl a, 4" 3149 +d "shl a, 5" 3159 +d "shl a, 6" 3169 +d "shl a, 7" 3179 +d "shl b, 1" 3118 +d "shl b, 2" 3128 +d "shl b, 3" 3138 +d "shl b, 4" 3148 +d "shl b, 5" 3158 +d "shl b, 6" 3168 +d "shl b, 7" 3178 +d "shl c, 1" 3117 +d "shl c, 2" 3127 +d "shl c, 3" 3137 +d "shl c, 4" 3147 +d "shl c, 5" 3157 +d "shl c, 6" 3167 +d "shl c, 7" 3177 +d "shlw ax, 1" 311d +d "shlw ax, 2" 312d +d "shlw ax, 3" 313d +d "shlw ax, 4" 314d +d "shlw ax, 5" 315d +d "shlw ax, 6" 316d +d "shlw ax, 7" 317d +d "shlw ax, 8" 318d +d "shlw ax, 9" 319d +d "shlw ax, 10" 31ad +d "shlw ax, 11" 31bd +d "shlw ax, 12" 31cd +d "shlw ax, 13" 31dd +d "shlw ax, 14" 31ed +d "shlw ax, 15" 31fd +d "shlw bc, 1" 311c +d "shlw bc, 2" 312c +d "shlw bc, 3" 313c +d "shlw bc, 4" 314c +d "shlw bc, 5" 315c +d "shlw bc, 6" 316c +d "shlw bc, 7" 317c +d "shlw bc, 8" 318c +d "shlw bc, 9" 319c +d "shlw bc, 10" 31ac +d "shlw bc, 11" 31bc +d "shlw bc, 12" 31cc +d "shlw bc, 13" 31dc +d "shlw bc, 14" 31ec +d "shlw bc, 15" 31fc +d "sar a, 1" 311b +d "sar a, 2" 312b +d "sar a, 3" 313b +d "sar a, 4" 314b +d "sar a, 5" 315b +d "sar a, 6" 316b +d "sar a, 7" 317b +d "sarw ax, 1" 311f +d "sarw ax, 2" 312f +d "sarw ax, 3" 313f +d "sarw ax, 4" 314f +d "sarw ax, 5" 315f +d "sarw ax, 6" 316f +d "sarw ax, 7" 317f +d "sarw ax, 8" 318f +d "sarw ax, 9" 319f +d "sarw ax, 10" 31af +d "sarw ax, 11" 31bf +d "sarw ax, 12" 31cf +d "sarw ax, 13" 31df +d "sarw ax, 14" 31ef +d "sarw ax, 15" 31ff +d "ror a, 1" 61db +d "rol a, 1" 61eb +d "rorc a, 1" 61fb +d "rolc a, 1" 61dc +d "rolwc ax, 1" 61ee +d "rolwc bc, 1" 61fe +d "mov1 cy, 0xffe46.0" 710426 +d "mov1 cy, 0xffe46.1" 711426 +d "mov1 cy, 0xffe46.2" 712426 +d "mov1 cy, 0xffe46.3" 713426 +d "mov1 cy, 0xffe46.4" 714426 +d "mov1 cy, 0xffe46.5" 715426 +d "mov1 cy, 0xffe46.6" 716426 +d "mov1 cy, 0xffe46.7" 717426 +d "mov1 cy, pmc.0" 710cfe +d "mov1 cy, pmc.1" 711cfe +d "mov1 cy, pmc.2" 712cfe +d "mov1 cy, pmc.3" 713cfe +d "mov1 cy, pmc.4" 714cfe +d "mov1 cy, pmc.5" 715cfe +d "mov1 cy, pmc.6" 716cfe +d "mov1 cy, pmc.7" 717cfe +d "mov1 cy, a.0" 718c +d "mov1 cy, a.1" 719c +d "mov1 cy, a.2" 71ac +d "mov1 cy, a.3" 71bc +d "mov1 cy, a.4" 71cc +d "mov1 cy, a.5" 71dc +d "mov1 cy, a.6" 71ec +d "mov1 cy, a.7" 71fc +d "mov1 cy, psw.0" 710cfa +d "mov1 cy, psw.1" 711cfa +d "mov1 cy, psw.2" 712cfa +d "mov1 cy, psw.3" 713cfa +d "mov1 cy, psw.4" 714cfa +d "mov1 cy, psw.5" 715cfa +d "mov1 cy, psw.6" 716cfa +d "mov1 cy, psw.7" 717cfa +d "mov1 cy, [hl].0" 7184 +d "mov1 cy, [hl].1" 7194 +d "mov1 cy, [hl].2" 71a4 +d "mov1 cy, [hl].3" 71b4 +d "mov1 cy, [hl].4" 71c4 +d "mov1 cy, [hl].5" 71d4 +d "mov1 cy, [hl].6" 71e4 +d "mov1 cy, [hl].7" 71f4 +d "mov1 0xffe46.0, cy" 710126 +d "mov1 0xffe46.1, cy" 711126 +d "mov1 0xffe46.2, cy" 712126 +d "mov1 0xffe46.3, cy" 713126 +d "mov1 0xffe46.4, cy" 714126 +d "mov1 0xffe46.5, cy" 715126 +d "mov1 0xffe46.6, cy" 716126 +d "mov1 0xffe46.7, cy" 717126 +d "mov1 pmc.0, cy" 7109fe +d "mov1 pmc.1, cy" 7119fe +d "mov1 pmc.2, cy" 7129fe +d "mov1 pmc.3, cy" 7139fe +d "mov1 pmc.4, cy" 7149fe +d "mov1 pmc.5, cy" 7159fe +d "mov1 pmc.6, cy" 7169fe +d "mov1 pmc.7, cy" 7179fe +d "mov1 a.0, cy" 7189 +d "mov1 a.1, cy" 7199 +d "mov1 a.2, cy" 71a9 +d "mov1 a.3, cy" 71b9 +d "mov1 a.4, cy" 71c9 +d "mov1 a.5, cy" 71d9 +d "mov1 a.6, cy" 71e9 +d "mov1 a.7, cy" 71f9 +d "mov1 psw.0, cy" 7109fa +d "mov1 psw.1, cy" 7119fa +d "mov1 psw.2, cy" 7129fa +d "mov1 psw.3, cy" 7139fa +d "mov1 psw.4, cy" 7149fa +d "mov1 psw.5, cy" 7159fa +d "mov1 psw.6, cy" 7169fa +d "mov1 psw.7, cy" 7179fa +d "mov1 [hl].0, cy" 7181 +d "mov1 [hl].1, cy" 7191 +d "mov1 [hl].2, cy" 71a1 +d "mov1 [hl].3, cy" 71b1 +d "mov1 [hl].4, cy" 71c1 +d "mov1 [hl].5, cy" 71d1 +d "mov1 [hl].6, cy" 71e1 +d "mov1 [hl].7, cy" 71f1 +d "mov1 cy, es:[hl].0" 117184 +d "mov1 cy, es:[hl].1" 117194 +d "mov1 cy, es:[hl].2" 1171a4 +d "mov1 cy, es:[hl].3" 1171b4 +d "mov1 cy, es:[hl].4" 1171c4 +d "mov1 cy, es:[hl].5" 1171d4 +d "mov1 cy, es:[hl].6" 1171e4 +d "mov1 cy, es:[hl].7" 1171f4 +d "mov1 es:[hl].0, cy" 117181 +d "mov1 es:[hl].1, cy" 117191 +d "mov1 es:[hl].2, cy" 1171a1 +d "mov1 es:[hl].3, cy" 1171b1 +d "mov1 es:[hl].4, cy" 1171c1 +d "mov1 es:[hl].5, cy" 1171d1 +d "mov1 es:[hl].6, cy" 1171e1 +d "mov1 es:[hl].7, cy" 1171f1 +d "and1 cy, 0xffe46.0" 710526 +d "and1 cy, 0xffe46.1" 711526 +d "and1 cy, 0xffe46.2" 712526 +d "and1 cy, 0xffe46.3" 713526 +d "and1 cy, 0xffe46.4" 714526 +d "and1 cy, 0xffe46.5" 715526 +d "and1 cy, 0xffe46.6" 716526 +d "and1 cy, 0xffe46.7" 717526 +d "and1 cy, pmc.0" 710dfe +d "and1 cy, pmc.1" 711dfe +d "and1 cy, pmc.2" 712dfe +d "and1 cy, pmc.3" 713dfe +d "and1 cy, pmc.4" 714dfe +d "and1 cy, pmc.5" 715dfe +d "and1 cy, pmc.6" 716dfe +d "and1 cy, pmc.7" 717dfe +d "and1 cy, a.0" 718d +d "and1 cy, a.1" 719d +d "and1 cy, a.2" 71ad +d "and1 cy, a.3" 71bd +d "and1 cy, a.4" 71cd +d "and1 cy, a.5" 71dd +d "and1 cy, a.6" 71ed +d "and1 cy, a.7" 71fd +d "and1 cy, psw.0" 710dfa +d "and1 cy, psw.1" 711dfa +d "and1 cy, psw.2" 712dfa +d "and1 cy, psw.3" 713dfa +d "and1 cy, psw.4" 714dfa +d "and1 cy, psw.5" 715dfa +d "and1 cy, psw.6" 716dfa +d "and1 cy, psw.7" 717dfa +d "and1 cy, [hl].0" 7185 +d "and1 cy, [hl].1" 7195 +d "and1 cy, [hl].2" 71a5 +d "and1 cy, [hl].3" 71b5 +d "and1 cy, [hl].4" 71c5 +d "and1 cy, [hl].5" 71d5 +d "and1 cy, [hl].6" 71e5 +d "and1 cy, [hl].7" 71f5 +d "and1 cy, es:[hl].0" 117185 +d "and1 cy, es:[hl].1" 117195 +d "and1 cy, es:[hl].2" 1171a5 +d "and1 cy, es:[hl].3" 1171b5 +d "and1 cy, es:[hl].4" 1171c5 +d "and1 cy, es:[hl].5" 1171d5 +d "and1 cy, es:[hl].6" 1171e5 +d "and1 cy, es:[hl].7" 1171f5 +d "or1 cy, 0xffe46.0" 710626 +d "or1 cy, 0xffe46.1" 711626 +d "or1 cy, 0xffe46.2" 712626 +d "or1 cy, 0xffe46.3" 713626 +d "or1 cy, 0xffe46.4" 714626 +d "or1 cy, 0xffe46.5" 715626 +d "or1 cy, 0xffe46.6" 716626 +d "or1 cy, 0xffe46.7" 717626 +d "or1 cy, pmc.0" 710efe +d "or1 cy, pmc.1" 711efe +d "or1 cy, pmc.2" 712efe +d "or1 cy, pmc.3" 713efe +d "or1 cy, pmc.4" 714efe +d "or1 cy, pmc.5" 715efe +d "or1 cy, pmc.6" 716efe +d "or1 cy, pmc.7" 717efe +d "or1 cy, a.0" 718e +d "or1 cy, a.1" 719e +d "or1 cy, a.2" 71ae +d "or1 cy, a.3" 71be +d "or1 cy, a.4" 71ce +d "or1 cy, a.5" 71de +d "or1 cy, a.6" 71ee +d "or1 cy, a.7" 71fe +d "or1 cy, psw.0" 710efa +d "or1 cy, psw.1" 711efa +d "or1 cy, psw.2" 712efa +d "or1 cy, psw.3" 713efa +d "or1 cy, psw.4" 714efa +d "or1 cy, psw.5" 715efa +d "or1 cy, psw.6" 716efa +d "or1 cy, psw.7" 717efa +d "or1 cy, [hl].0" 7186 +d "or1 cy, [hl].1" 7196 +d "or1 cy, [hl].2" 71a6 +d "or1 cy, [hl].3" 71b6 +d "or1 cy, [hl].4" 71c6 +d "or1 cy, [hl].5" 71d6 +d "or1 cy, [hl].6" 71e6 +d "or1 cy, [hl].7" 71f6 +d "or1 cy, es:[hl].0" 117186 +d "or1 cy, es:[hl].1" 117196 +d "or1 cy, es:[hl].2" 1171a6 +d "or1 cy, es:[hl].3" 1171b6 +d "or1 cy, es:[hl].4" 1171c6 +d "or1 cy, es:[hl].5" 1171d6 +d "or1 cy, es:[hl].6" 1171e6 +d "or1 cy, es:[hl].7" 1171f6 +d "xor1 cy, 0xffe46.0" 710726 +d "xor1 cy, 0xffe46.1" 711726 +d "xor1 cy, 0xffe46.2" 712726 +d "xor1 cy, 0xffe46.3" 713726 +d "xor1 cy, 0xffe46.4" 714726 +d "xor1 cy, 0xffe46.5" 715726 +d "xor1 cy, 0xffe46.6" 716726 +d "xor1 cy, 0xffe46.7" 717726 +d "xor1 cy, pmc.0" 710ffe +d "xor1 cy, pmc.1" 711ffe +d "xor1 cy, pmc.2" 712ffe +d "xor1 cy, pmc.3" 713ffe +d "xor1 cy, pmc.4" 714ffe +d "xor1 cy, pmc.5" 715ffe +d "xor1 cy, pmc.6" 716ffe +d "xor1 cy, pmc.7" 717ffe +d "xor1 cy, a.0" 718f +d "xor1 cy, a.1" 719f +d "xor1 cy, a.2" 71af +d "xor1 cy, a.3" 71bf +d "xor1 cy, a.4" 71cf +d "xor1 cy, a.5" 71df +d "xor1 cy, a.6" 71ef +d "xor1 cy, a.7" 71ff +d "xor1 cy, psw.0" 710ffa +d "xor1 cy, psw.1" 711ffa +d "xor1 cy, psw.2" 712ffa +d "xor1 cy, psw.3" 713ffa +d "xor1 cy, psw.4" 714ffa +d "xor1 cy, psw.5" 715ffa +d "xor1 cy, psw.6" 716ffa +d "xor1 cy, psw.7" 717ffa +d "xor1 cy, [hl].0" 7187 +d "xor1 cy, [hl].1" 7197 +d "xor1 cy, [hl].2" 71a7 +d "xor1 cy, [hl].3" 71b7 +d "xor1 cy, [hl].4" 71c7 +d "xor1 cy, [hl].5" 71d7 +d "xor1 cy, [hl].6" 71e7 +d "xor1 cy, [hl].7" 71f7 +d "xor1 cy, es:[hl].0" 117187 +d "xor1 cy, es:[hl].1" 117197 +d "xor1 cy, es:[hl].2" 1171a7 +d "xor1 cy, es:[hl].3" 1171b7 +d "xor1 cy, es:[hl].4" 1171c7 +d "xor1 cy, es:[hl].5" 1171d7 +d "xor1 cy, es:[hl].6" 1171e7 +d "xor1 cy, es:[hl].7" 1171f7 +d "set1 0xffe46.0" 710226 +d "set1 0xffe46.1" 711226 +d "set1 0xffe46.2" 712226 +d "set1 0xffe46.3" 713226 +d "set1 0xffe46.4" 714226 +d "set1 0xffe46.5" 715226 +d "set1 0xffe46.6" 716226 +d "set1 0xffe46.7" 717226 +d "set1 pmc.0" 710afe +d "set1 pmc.1" 711afe +d "set1 pmc.2" 712afe +d "set1 pmc.3" 713afe +d "set1 pmc.4" 714afe +d "set1 pmc.5" 715afe +d "set1 pmc.6" 716afe +d "set1 pmc.7" 717afe +d "set1 a.0" 718a +d "set1 a.1" 719a +d "set1 a.2" 71aa +d "set1 a.3" 71ba +d "set1 a.4" 71ca +d "set1 a.5" 71da +d "set1 a.6" 71ea +d "set1 a.7" 71fa +d "set1 !0x30a4.0" 7100a430 +d "set1 !0x30a4.1" 7110a430 +d "set1 !0x30a4.2" 7120a430 +d "set1 !0x30a4.3" 7130a430 +d "set1 !0x30a4.4" 7140a430 +d "set1 !0x30a4.5" 7150a430 +d "set1 !0x30a4.6" 7160a430 +d "set1 !0x30a4.7" 7170a430 +d "set1 psw.0" 710afa +d "set1 psw.1" 711afa +d "set1 psw.2" 712afa +d "set1 psw.3" 713afa +d "set1 psw.4" 714afa +d "set1 psw.5" 715afa +d "set1 psw.6" 716afa +# d "set1 psw.7" 717afa enable interrupt (see end of file) +d "set1 [hl].0" 7182 +d "set1 [hl].1" 7192 +d "set1 [hl].2" 71a2 +d "set1 [hl].3" 71b2 +d "set1 [hl].4" 71c2 +d "set1 [hl].5" 71d2 +d "set1 [hl].6" 71e2 +d "set1 [hl].7" 71f2 +d "set1 es:!0x30a4.0" 117100a430 +d "set1 es:!0x30a4.1" 117110a430 +d "set1 es:!0x30a4.2" 117120a430 +d "set1 es:!0x30a4.3" 117130a430 +d "set1 es:!0x30a4.4" 117140a430 +d "set1 es:!0x30a4.5" 117150a430 +d "set1 es:!0x30a4.6" 117160a430 +d "set1 es:!0x30a4.7" 117170a430 +d "set1 es:[hl].0" 117182 +d "set1 es:[hl].1" 117192 +d "set1 es:[hl].2" 1171a2 +d "set1 es:[hl].3" 1171b2 +d "set1 es:[hl].4" 1171c2 +d "set1 es:[hl].5" 1171d2 +d "set1 es:[hl].6" 1171e2 +d "set1 es:[hl].7" 1171f2 +d "clr1 0xffe46.0" 710326 +d "clr1 0xffe46.1" 711326 +d "clr1 0xffe46.2" 712326 +d "clr1 0xffe46.3" 713326 +d "clr1 0xffe46.4" 714326 +d "clr1 0xffe46.5" 715326 +d "clr1 0xffe46.6" 716326 +d "clr1 0xffe46.7" 717326 +d "clr1 pmc.0" 710bfe +d "clr1 pmc.1" 711bfe +d "clr1 pmc.2" 712bfe +d "clr1 pmc.3" 713bfe +d "clr1 pmc.4" 714bfe +d "clr1 pmc.5" 715bfe +d "clr1 pmc.6" 716bfe +d "clr1 pmc.7" 717bfe +d "clr1 a.0" 718b +d "clr1 a.1" 719b +d "clr1 a.2" 71ab +d "clr1 a.3" 71bb +d "clr1 a.4" 71cb +d "clr1 a.5" 71db +d "clr1 a.6" 71eb +d "clr1 a.7" 71fb +d "clr1 !0x30a4.0" 7108a430 +d "clr1 !0x30a4.1" 7118a430 +d "clr1 !0x30a4.2" 7128a430 +d "clr1 !0x30a4.3" 7138a430 +d "clr1 !0x30a4.4" 7148a430 +d "clr1 !0x30a4.5" 7158a430 +d "clr1 !0x30a4.6" 7168a430 +d "clr1 !0x30a4.7" 7178a430 +d "clr1 psw.0" 710bfa +d "clr1 psw.1" 711bfa +d "clr1 psw.2" 712bfa +d "clr1 psw.3" 713bfa +d "clr1 psw.4" 714bfa +d "clr1 psw.5" 715bfa +d "clr1 psw.6" 716bfa +# d "clr1 psw.7" 717bfa disable interrupt (see end of file) +d "clr1 [hl].0" 7183 +d "clr1 [hl].1" 7193 +d "clr1 [hl].2" 71a3 +d "clr1 [hl].3" 71b3 +d "clr1 [hl].4" 71c3 +d "clr1 [hl].5" 71d3 +d "clr1 [hl].6" 71e3 +d "clr1 [hl].7" 71f3 +d "clr1 es:!0x30a4.0" 117108a430 +d "clr1 es:!0x30a4.1" 117118a430 +d "clr1 es:!0x30a4.2" 117128a430 +d "clr1 es:!0x30a4.3" 117138a430 +d "clr1 es:!0x30a4.4" 117148a430 +d "clr1 es:!0x30a4.5" 117158a430 +d "clr1 es:!0x30a4.6" 117168a430 +d "clr1 es:!0x30a4.7" 117178a430 +d "clr1 es:[hl].0" 117183 +d "clr1 es:[hl].1" 117193 +d "clr1 es:[hl].2" 1171a3 +d "clr1 es:[hl].3" 1171b3 +d "clr1 es:[hl].4" 1171c3 +d "clr1 es:[hl].5" 1171d3 +d "clr1 es:[hl].6" 1171e3 +d "clr1 es:[hl].7" 1171f3 +d "set1 cy" 7180 +d "clr1 cy" 7188 +d "not1 cy" 71c0 +d "call ax" 61ca +d "call bc" 61da +d "call de" 61ea +d "call hl" 61fa +d "call $!0xfa20" fe20fa +d "call !0x30a4" fda430 +d "call !!0xffa20" fc20fa0f +d "callt [0x80]" 6184 +d "callt [0x82]" 6194 +d "callt [0x84]" 61a4 +d "callt [0x86]" 61b4 +d "callt [0x88]" 61c4 +d "callt [0x8a]" 61d4 +d "callt [0x8c]" 61e4 +d "callt [0x8e]" 61f4 +d "callt [0x90]" 6185 +d "callt [0x92]" 6195 +d "callt [0x94]" 61a5 +d "callt [0x96]" 61b5 +d "callt [0x98]" 61c5 +d "callt [0x9a]" 61d5 +d "callt [0x9c]" 61e5 +d "callt [0x9e]" 61f5 +d "callt [0xa0]" 6186 +d "callt [0xa2]" 6196 +d "callt [0xa4]" 61a6 +d "callt [0xa6]" 61b6 +d "callt [0xa8]" 61c6 +d "callt [0xaa]" 61d6 +d "callt [0xac]" 61e6 +d "callt [0xae]" 61f6 +d "callt [0xb0]" 6187 +d "callt [0xb2]" 6197 +d "callt [0xb4]" 61a7 +d "callt [0xb6]" 61b7 +d "callt [0xb8]" 61c7 +d "callt [0xba]" 61d7 +d "callt [0xbc]" 61e7 +d "callt [0xbe]" 61f7 +d "brk" 61cc +d "ret" d7 +d "reti" 61fc +d "retb" 61ec +d "push psw" 61dd +d "push ax" c1 +d "push bc" c3 +d "push de" c5 +d "push hl" c7 +d "pop psw" 61cd +d "pop ax" c0 +d "pop bc" c2 +d "pop de" c4 +d "pop hl" c6 +d "movw spl, #0x1337" cbf83713 +d "movw spl, ax" bef8 +d "movw ax, spl" aef8 +d "movw bc, !0xfa20" db20fa +d "movw de, !0xfa20" eb20fa +d "movw hl, !0xfa20" fb20fa +d "addw sp, #0x30" 1030 +d "subw sp, #0x30" 2030 +d "br ax" 61cb +d "br $0x30" ef30 +d "br $!0xfa20" ee20fa +d "br !0x30a4" eda430 +d "br !!0xffa20" ec20fa0f +d "bc $0x30" dc30 +d "bnc $0x30" de30 +d "bz $0x30" dd30 +d "bnz $0x30" df30 +d "bh $0x30" 61c330 +d "bnh $0x30" 61d330 +d "bt 0xffe46.0, $0x30" 31022630 +d "bt 0xffe46.1, $0x30" 31122630 +d "bt 0xffe46.2, $0x30" 31222630 +d "bt 0xffe46.3, $0x30" 31322630 +d "bt 0xffe46.4, $0x30" 31422630 +d "bt 0xffe46.5, $0x30" 31522630 +d "bt 0xffe46.6, $0x30" 31622630 +d "bt 0xffe46.7, $0x30" 31722630 +d "bt pmc.0, $0x30" 3182fe30 +d "bt pmc.1, $0x30" 3192fe30 +d "bt pmc.2, $0x30" 31a2fe30 +d "bt pmc.3, $0x30" 31b2fe30 +d "bt pmc.4, $0x30" 31c2fe30 +d "bt pmc.5, $0x30" 31d2fe30 +d "bt pmc.6, $0x30" 31e2fe30 +d "bt pmc.7, $0x30" 31f2fe30 +d "bt a.0, $0x30" 310330 +d "bt a.1, $0x30" 311330 +d "bt a.2, $0x30" 312330 +d "bt a.3, $0x30" 313330 +d "bt a.4, $0x30" 314330 +d "bt a.5, $0x30" 315330 +d "bt a.6, $0x30" 316330 +d "bt a.7, $0x30" 317330 +d "bt psw.0, $0x30" 3182fa30 +d "bt psw.1, $0x30" 3192fa30 +d "bt psw.2, $0x30" 31a2fa30 +d "bt psw.3, $0x30" 31b2fa30 +d "bt psw.4, $0x30" 31c2fa30 +d "bt psw.5, $0x30" 31d2fa30 +d "bt psw.6, $0x30" 31e2fa30 +d "bt psw.7, $0x30" 31f2fa30 +d "bt [hl].0, $0x30" 318330 +d "bt [hl].1, $0x30" 319330 +d "bt [hl].2, $0x30" 31a330 +d "bt [hl].3, $0x30" 31b330 +d "bt [hl].4, $0x30" 31c330 +d "bt [hl].5, $0x30" 31d330 +d "bt [hl].6, $0x30" 31e330 +d "bt [hl].7, $0x30" 31f330 +d "bt es:[hl].0, $0x30" 11318330 +d "bt es:[hl].1, $0x30" 11319330 +d "bt es:[hl].2, $0x30" 1131a330 +d "bt es:[hl].3, $0x30" 1131b330 +d "bt es:[hl].4, $0x30" 1131c330 +d "bt es:[hl].5, $0x30" 1131d330 +d "bt es:[hl].6, $0x30" 1131e330 +d "bt es:[hl].7, $0x30" 1131f330 +d "bf 0xffe46.0, $0x30" 31042630 +d "bf 0xffe46.1, $0x30" 31142630 +d "bf 0xffe46.2, $0x30" 31242630 +d "bf 0xffe46.3, $0x30" 31342630 +d "bf 0xffe46.4, $0x30" 31442630 +d "bf 0xffe46.5, $0x30" 31542630 +d "bf 0xffe46.6, $0x30" 31642630 +d "bf 0xffe46.7, $0x30" 31742630 +d "bf pmc.0, $0x30" 3184fe30 +d "bf pmc.1, $0x30" 3194fe30 +d "bf pmc.2, $0x30" 31a4fe30 +d "bf pmc.3, $0x30" 31b4fe30 +d "bf pmc.4, $0x30" 31c4fe30 +d "bf pmc.5, $0x30" 31d4fe30 +d "bf pmc.6, $0x30" 31e4fe30 +d "bf pmc.7, $0x30" 31f4fe30 +d "bf a.0, $0x30" 310530 +d "bf a.1, $0x30" 311530 +d "bf a.2, $0x30" 312530 +d "bf a.3, $0x30" 313530 +d "bf a.4, $0x30" 314530 +d "bf a.5, $0x30" 315530 +d "bf a.6, $0x30" 316530 +d "bf a.7, $0x30" 317530 +d "bf psw.0, $0x30" 3184fa30 +d "bf psw.1, $0x30" 3194fa30 +d "bf psw.2, $0x30" 31a4fa30 +d "bf psw.3, $0x30" 31b4fa30 +d "bf psw.4, $0x30" 31c4fa30 +d "bf psw.5, $0x30" 31d4fa30 +d "bf psw.6, $0x30" 31e4fa30 +d "bf psw.7, $0x30" 31f4fa30 +d "bf [hl].0, $0x30" 318530 +d "bf [hl].1, $0x30" 319530 +d "bf [hl].2, $0x30" 31a530 +d "bf [hl].3, $0x30" 31b530 +d "bf [hl].4, $0x30" 31c530 +d "bf [hl].5, $0x30" 31d530 +d "bf [hl].6, $0x30" 31e530 +d "bf [hl].7, $0x30" 31f530 +d "bf es:[hl].0, $0x30" 11318530 +d "bf es:[hl].1, $0x30" 11319530 +d "bf es:[hl].2, $0x30" 1131a530 +d "bf es:[hl].3, $0x30" 1131b530 +d "bf es:[hl].4, $0x30" 1131c530 +d "bf es:[hl].5, $0x30" 1131d530 +d "bf es:[hl].6, $0x30" 1131e530 +d "bf es:[hl].7, $0x30" 1131f530 +d "btclr 0xffe46.0, $0x30" 31002630 +d "btclr 0xffe46.1, $0x30" 31102630 +d "btclr 0xffe46.2, $0x30" 31202630 +d "btclr 0xffe46.3, $0x30" 31302630 +d "btclr 0xffe46.4, $0x30" 31402630 +d "btclr 0xffe46.5, $0x30" 31502630 +d "btclr 0xffe46.6, $0x30" 31602630 +d "btclr 0xffe46.7, $0x30" 31702630 +d "btclr pmc.0, $0x30" 3180fe30 +d "btclr pmc.1, $0x30" 3190fe30 +d "btclr pmc.2, $0x30" 31a0fe30 +d "btclr pmc.3, $0x30" 31b0fe30 +d "btclr pmc.4, $0x30" 31c0fe30 +d "btclr pmc.5, $0x30" 31d0fe30 +d "btclr pmc.6, $0x30" 31e0fe30 +d "btclr pmc.7, $0x30" 31f0fe30 +d "btclr a.0, $0x30" 310130 +d "btclr a.1, $0x30" 311130 +d "btclr a.2, $0x30" 312130 +d "btclr a.3, $0x30" 313130 +d "btclr a.4, $0x30" 314130 +d "btclr a.5, $0x30" 315130 +d "btclr a.6, $0x30" 316130 +d "btclr a.7, $0x30" 317130 +d "btclr psw.0, $0x30" 3180fa30 +d "btclr psw.1, $0x30" 3190fa30 +d "btclr psw.2, $0x30" 31a0fa30 +d "btclr psw.3, $0x30" 31b0fa30 +d "btclr psw.4, $0x30" 31c0fa30 +d "btclr psw.5, $0x30" 31d0fa30 +d "btclr psw.6, $0x30" 31e0fa30 +d "btclr psw.7, $0x30" 31f0fa30 +d "btclr [hl].0, $0x30" 318130 +d "btclr [hl].1, $0x30" 319130 +d "btclr [hl].2, $0x30" 31a130 +d "btclr [hl].3, $0x30" 31b130 +d "btclr [hl].4, $0x30" 31c130 +d "btclr [hl].5, $0x30" 31d130 +d "btclr [hl].6, $0x30" 31e130 +d "btclr [hl].7, $0x30" 31f130 +d "btclr es:[hl].0, $0x30" 11318130 +d "btclr es:[hl].1, $0x30" 11319130 +d "btclr es:[hl].2, $0x30" 1131a130 +d "btclr es:[hl].3, $0x30" 1131b130 +d "btclr es:[hl].4, $0x30" 1131c130 +d "btclr es:[hl].5, $0x30" 1131d130 +d "btclr es:[hl].6, $0x30" 1131e130 +d "btclr es:[hl].7, $0x30" 1131f130 +d "skc" 61c8 +d "sknc" 61d8 +d "skz" 61e8 +d "sknz" 61f8 +d "skh" 61e3 +d "sknh" 61f3 +d "sel rb0" 61cf +d "sel rb1" 61df +d "sel rb2" 61ef +d "sel rb3" 61ff +d "nop" 00 +d "ei" 717afa +d "di" 717bfa +d "halt" 61ed +d "stop" 61fd + +# test 'holes' +d "(invalid)" 21 +d "(invalid)" ff +d "(invalid)" 6119 +d "(invalid)" 6139 +d "(invalid)" 6181 +d "(invalid)" 6183 +d "(invalid)" 6188 +d "(invalid)" 6191 +d "(invalid)" 6193 +d "(invalid)" 6198 +d "(invalid)" 6191 +d "(invalid)" 6193 +d "(invalid)" 6198 +d "(invalid)" 6199 +d "(invalid)" 619a +d "(invalid)" 619b +d "(invalid)" 619c +d "(invalid)" 619d +d "(invalid)" 619e +d "(invalid)" 619f +d "(invalid)" 61a1 +d "(invalid)" 61a3 +d "(invalid)" 61b1 +d "(invalid)" 61b3 +d "(invalid)" 61ba +d "(invalid)" 61bb +d "(invalid)" 61bc +d "(invalid)" 61bd +d "(invalid)" 61be +d "(invalid)" 61bf +d "(invalid)" 61c1 +d "(invalid)" 61d1 +d "(invalid)" 61e1 +d "(invalid)" 61f1 +d "(invalid)" 7190 +d "(invalid)" 7198 +d "(invalid)" 71a0 +d "(invalid)" 71a8 +d "(invalid)" 71b0 +d "(invalid)" 71b8 +d "(invalid)" 71c8 +d "(invalid)" 71d0 +d "(invalid)" 71d0 +d "(invalid)" 71e0 +d "(invalid)" 71e8 +d "(invalid)" 71f8 +d "(invalid)" 3106 +d "(invalid)" 3107 +d "(invalid)" 3108 +d "(invalid)" 3109 +d "(invalid)" 310a +d "(invalid)" 310b +d "(invalid)" 310c +d "(invalid)" 310d +d "(invalid)" 310e +d "(invalid)" 310f +d "(invalid)" 3116 +d "(invalid)" 3126 +d "(invalid)" 3136 +d "(invalid)" 3146 +d "(invalid)" 3156 +d "(invalid)" 3166 +d "(invalid)" 3176 +d "(invalid)" 3186 +d "(invalid)" 3186 +d "(invalid)" 3187 +d "(invalid)" 3188 +d "(invalid)" 3189 +d "(invalid)" 318a +d "(invalid)" 318b +d "(invalid)" 3197 +d "(invalid)" 3198 +d "(invalid)" 3199 +d "(invalid)" 319a +d "(invalid)" 319b +d "(invalid)" 31a7 +d "(invalid)" 31a8 +d "(invalid)" 31a9 +d "(invalid)" 31aa +d "(invalid)" 31ab +d "(invalid)" 31b7 +d "(invalid)" 31b8 +d "(invalid)" 31b9 +d "(invalid)" 31ba +d "(invalid)" 31bb +d "(invalid)" 31c7 +d "(invalid)" 31c8 +d "(invalid)" 31c9 +d "(invalid)" 31ca +d "(invalid)" 31cb +d "(invalid)" 31d7 +d "(invalid)" 31d8 +d "(invalid)" 31d9 +d "(invalid)" 31da +d "(invalid)" 31db +d "(invalid)" 31e7 +d "(invalid)" 31e8 +d "(invalid)" 31e9 +d "(invalid)" 31ea +d "(invalid)" 31eb +d "(invalid)" 31f7 +d "(invalid)" 31f8 +d "(invalid)" 31f9 +d "(invalid)" 31fa +d "(invalid)" 31fb diff --git a/test/db/cmd/cmd_list b/test/db/cmd/cmd_list index b5aaf8cc9e3..11cde8ca77b 100644 --- a/test/db/cmd/cmd_list +++ b/test/db/cmd/cmd_list @@ -418,6 +418,7 @@ a___ 32 64 ppc.as LGPL3 as PPC Assembler (use RZ_PPC_AS environment _dAe 32 64 ppc BSD Capstone PowerPC disassembler (by pancake) _dA_ 32 propeller LGPL3 propeller disassembly plugin _dA_ 8 16 pyc LGPL3 PYC disassemble plugin +adA_ 32 rl78 LGPL3 Renesas RL78 disassembler (by Bastian Engel) _dA_ 32 rsp LGPL3 Reality Signal Processor adAe 32 sh LGPL3 SuperH-4 CPU (by DMaroo) _dA_ 8 16 snes LGPL3 SuperNES CPU @@ -491,6 +492,7 @@ ppc.as ppc propeller pyc +rl78 rsp sh snes @@ -528,7 +530,7 @@ NAME=Print the asm/analysis plugins in JSON FILE== CMDS=Laj EXPECT=<