diff --git a/librz/analysis/arch/hexagon/hexagon_il.c b/librz/analysis/arch/hexagon/hexagon_il.c index e30bce6e849..48bd5799a11 100644 --- a/librz/analysis/arch/hexagon/hexagon_il.c +++ b/librz/analysis/arch/hexagon/hexagon_il.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 15:00:15-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -643,13 +643,17 @@ static inline bool read_cond_faulty(RzILOpPure *low_val, RzILOpPure *high_val, u } /** - * \brief Checks for rw registers (e.g. Rx) if read and writes overlap. + * \brief Checks for rw registers (e.g. Rx) if reads and writes overlap. * - * \returns true If the register is a "x" register and the read and write flag was set. - * \returns false Otherwise. + * \param pkt The packet of the current instruction. + * \param op The operand to check. + * \param reg_num The number of the register to check. + * + * \return true If the register is a "x" register and it was read and written before. + * \return false Otherwise. */ static bool x_reg_rw_overlap(const HexPkt *pkt, const HexOp *op, ut32 reg_num) { - switch(op->class) { + switch (op->class) { default: rz_warn_if_reached(); RZ_LOG_WARN("Checking rw overlap of class %d not implemented yet.", op->class); diff --git a/librz/analysis/arch/hexagon/hexagon_il.h b/librz/analysis/arch/hexagon/hexagon_il.h index e85208bfd90..12ca88c61b7 100644 --- a/librz/analysis/arch/hexagon/hexagon_il.h +++ b/librz/analysis/arch/hexagon/hexagon_il.h @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/hexagon_il_getter_table.h b/librz/analysis/arch/hexagon/hexagon_il_getter_table.h index 7ad459f7cec..faea2980066 100644 --- a/librz/analysis/arch/hexagon/hexagon_il_getter_table.h +++ b/librz/analysis/arch/hexagon/hexagon_il_getter_table.h @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c index b9a5069f913..6c3bb504b75 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 15:00:15-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -756,7 +756,7 @@ RzILOpEffect *hex_il_op_a2_addpsat(HexInsnPktBundle *bundle) { RzILOpPure *op_AND_17 = LOGAND(VARL("__xor"), VARL("__mask")); RzILOpEffect *branch_44 = BRANCH(NON_ZERO(op_AND_17), seq_then_42, seq_else_43); - RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44); return instruction_sequence; } @@ -2328,11 +2328,11 @@ RzILOpEffect *hex_il_op_a2_roundsat(HexInsnPktBundle *bundle) { RzILOpEffect *branch_43 = BRANCH(NON_ZERO(op_AND_17), seq_then_41, seq_else_42); // Rd = ((st32) ((st64) ((st32) ((tmp >> 0x20) & 0xffffffff)))); - RzILOpPure *op_RSHIFT_48 = SHIFTRA(VARL("tmp"), SN(32, 0x20)); - RzILOpPure *op_AND_50 = LOGAND(op_RSHIFT_48, SN(64, 0xffffffff)); - RzILOpEffect *op_ASSIGN_54 = WRITE_REG(bundle, Rd_op, CAST(32, MSB(CAST(64, MSB(CAST(32, MSB(op_AND_50), DUP(op_AND_50))), CAST(32, MSB(DUP(op_AND_50)), DUP(op_AND_50)))), CAST(64, MSB(CAST(32, MSB(DUP(op_AND_50)), DUP(op_AND_50))), CAST(32, MSB(DUP(op_AND_50)), DUP(op_AND_50))))); + RzILOpPure *op_RSHIFT_49 = SHIFTRA(VARL("tmp"), SN(32, 0x20)); + RzILOpPure *op_AND_51 = LOGAND(op_RSHIFT_49, SN(64, 0xffffffff)); + RzILOpEffect *op_ASSIGN_55 = WRITE_REG(bundle, Rd_op, CAST(32, MSB(CAST(64, MSB(CAST(32, MSB(op_AND_51), DUP(op_AND_51))), CAST(32, MSB(DUP(op_AND_51)), DUP(op_AND_51)))), CAST(64, MSB(CAST(32, MSB(DUP(op_AND_51)), DUP(op_AND_51))), CAST(32, MSB(DUP(op_AND_51)), DUP(op_AND_51))))); - RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_4, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_43, op_ASSIGN_54); + RzILOpEffect *instruction_sequence = SEQN(8, op_ASSIGN_4, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_43, EMPTY(), op_ASSIGN_55); return instruction_sequence; } @@ -6185,45 +6185,45 @@ RzILOpEffect *hex_il_op_a2_vcmpweq(HexInsnPktBundle *bundle) { RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43); // j = 0x4; - RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4)); + RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4)); // HYB(++j); - RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32)); + RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32)); // h_tmp69 = HYB(++j); - RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp69", VARL("j")); + RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp69", VARL("j")); // seq(h_tmp69 = HYB(++j); HYB(++j)); - RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49); + RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50); // Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) == ((st64) ((st32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j))); - RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j")); - RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54); - RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55); - RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20)); - RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff)); - RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20)); - RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff)); - RzILOpPure *op_EQ_75 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_64), DUP(op_AND_64))), CAST(32, MSB(DUP(op_AND_64)), DUP(op_AND_64))), CAST(64, MSB(CAST(32, MSB(op_AND_72), DUP(op_AND_72))), CAST(32, MSB(DUP(op_AND_72)), DUP(op_AND_72)))); - RzILOpPure *ite_cast_ut64_76 = ITE(op_EQ_75, UN(64, 1), UN(64, 0)); - RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j")); - RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77); - RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78)); + RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j")); + RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55); + RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56); + RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20)); + RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff)); + RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20)); + RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff)); + RzILOpPure *op_EQ_76 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_65), DUP(op_AND_65))), CAST(32, MSB(DUP(op_AND_65)), DUP(op_AND_65))), CAST(64, MSB(CAST(32, MSB(op_AND_73), DUP(op_AND_73))), CAST(32, MSB(DUP(op_AND_73)), DUP(op_AND_73)))); + RzILOpPure *ite_cast_ut64_77 = ITE(op_EQ_76, UN(64, 1), UN(64, 0)); + RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j")); + RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78); + RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79)); // seq(h_tmp69; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...; - RzILOpEffect *seq_82 = SEQN(2, op_ASSIGN_80, EMPTY()); + RzILOpEffect *seq_83 = SEQN(2, op_ASSIGN_81, EMPTY()); // seq(seq(h_tmp69; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...; - RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52); + RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53); // while ((j <= 0x7)) { seq(seq(h_tmp69; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... }; - RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7)); - RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83); + RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7)); + RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84); // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp69; Pd = ((st8) ( ...; - RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84); + RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85); - RzILOpEffect *instruction_sequence = SEQN(3, seq_44, seq_85, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(3, seq_44, EMPTY(), seq_86); return instruction_sequence; } @@ -6279,45 +6279,45 @@ RzILOpEffect *hex_il_op_a2_vcmpwgt(HexInsnPktBundle *bundle) { RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43); // j = 0x4; - RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4)); + RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4)); // HYB(++j); - RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32)); + RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32)); // h_tmp71 = HYB(++j); - RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp71", VARL("j")); + RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp71", VARL("j")); // seq(h_tmp71 = HYB(++j); HYB(++j)); - RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50); + RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49); // Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) > ((st64) ((st32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j))); - RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j")); - RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55); - RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56); - RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20)); - RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff)); - RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20)); - RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff)); - RzILOpPure *op_GT_76 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_65), DUP(op_AND_65))), CAST(32, MSB(DUP(op_AND_65)), DUP(op_AND_65))), CAST(64, MSB(CAST(32, MSB(op_AND_73), DUP(op_AND_73))), CAST(32, MSB(DUP(op_AND_73)), DUP(op_AND_73)))); - RzILOpPure *ite_cast_ut64_77 = ITE(op_GT_76, UN(64, 1), UN(64, 0)); - RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j")); - RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78); - RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79)); + RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j")); + RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54); + RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55); + RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20)); + RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff)); + RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20)); + RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff)); + RzILOpPure *op_GT_75 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_64), DUP(op_AND_64))), CAST(32, MSB(DUP(op_AND_64)), DUP(op_AND_64))), CAST(64, MSB(CAST(32, MSB(op_AND_72), DUP(op_AND_72))), CAST(32, MSB(DUP(op_AND_72)), DUP(op_AND_72)))); + RzILOpPure *ite_cast_ut64_76 = ITE(op_GT_75, UN(64, 1), UN(64, 0)); + RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j")); + RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77); + RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78)); // seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...; - RzILOpEffect *seq_83 = SEQN(2, op_ASSIGN_81, EMPTY()); + RzILOpEffect *seq_82 = SEQN(2, op_ASSIGN_80, EMPTY()); // seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...; - RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53); + RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52); // while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... }; - RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7)); - RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84); + RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7)); + RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83); // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ( ...; - RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85); + RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84); - RzILOpEffect *instruction_sequence = SEQN(3, seq_44, EMPTY(), seq_86); + RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_85); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c index 0fee495d7a6..dcc756418ce 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 15:00:15-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -2475,43 +2475,43 @@ RzILOpEffect *hex_il_op_a4_vcmpweqi(HexInsnPktBundle *bundle) { RzILOpEffect *seq_38 = SEQN(2, op_ASSIGN_2, for_37); // j = 0x4; - RzILOpEffect *op_ASSIGN_40 = SETL("j", SN(32, 4)); + RzILOpEffect *op_ASSIGN_41 = SETL("j", SN(32, 4)); // HYB(++j); - RzILOpEffect *op_INC_43 = SETL("j", INC(VARL("j"), 32)); + RzILOpEffect *op_INC_44 = SETL("j", INC(VARL("j"), 32)); // h_tmp134 = HYB(++j); - RzILOpEffect *op_ASSIGN_hybrid_tmp_45 = SETL("h_tmp134", VARL("j")); + RzILOpEffect *op_ASSIGN_hybrid_tmp_46 = SETL("h_tmp134", VARL("j")); // seq(h_tmp134 = HYB(++j); HYB(++j)); - RzILOpEffect *seq_46 = SEQN(2, op_ASSIGN_hybrid_tmp_45, op_INC_43); + RzILOpEffect *seq_47 = SEQN(2, op_ASSIGN_hybrid_tmp_46, op_INC_44); // Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) == ((st64) s)) ? 0x1 : 0x0) << j))); - RzILOpPure *op_LSHIFT_48 = SHIFTL0(UN(64, 1), VARL("j")); - RzILOpPure *op_NOT_49 = LOGNOT(op_LSHIFT_48); - RzILOpPure *op_AND_52 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_49); - RzILOpPure *op_RSHIFT_56 = SHIFTRA(DUP(Rss), SN(32, 0x20)); - RzILOpPure *op_AND_58 = LOGAND(op_RSHIFT_56, SN(64, 0xffffffff)); - RzILOpPure *op_EQ_62 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_58), DUP(op_AND_58))), CAST(32, MSB(DUP(op_AND_58)), DUP(op_AND_58))), CAST(64, MSB(VARL("s")), VARL("s"))); - RzILOpPure *ite_cast_ut64_63 = ITE(op_EQ_62, UN(64, 1), UN(64, 0)); - RzILOpPure *op_LSHIFT_64 = SHIFTL0(ite_cast_ut64_63, VARL("j")); - RzILOpPure *op_OR_65 = LOGOR(op_AND_52, op_LSHIFT_64); - RzILOpEffect *op_ASSIGN_67 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_65)); + RzILOpPure *op_LSHIFT_49 = SHIFTL0(UN(64, 1), VARL("j")); + RzILOpPure *op_NOT_50 = LOGNOT(op_LSHIFT_49); + RzILOpPure *op_AND_53 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_50); + RzILOpPure *op_RSHIFT_57 = SHIFTRA(DUP(Rss), SN(32, 0x20)); + RzILOpPure *op_AND_59 = LOGAND(op_RSHIFT_57, SN(64, 0xffffffff)); + RzILOpPure *op_EQ_63 = EQ(CAST(64, MSB(CAST(32, MSB(op_AND_59), DUP(op_AND_59))), CAST(32, MSB(DUP(op_AND_59)), DUP(op_AND_59))), CAST(64, MSB(VARL("s")), VARL("s"))); + RzILOpPure *ite_cast_ut64_64 = ITE(op_EQ_63, UN(64, 1), UN(64, 0)); + RzILOpPure *op_LSHIFT_65 = SHIFTL0(ite_cast_ut64_64, VARL("j")); + RzILOpPure *op_OR_66 = LOGOR(op_AND_53, op_LSHIFT_65); + RzILOpEffect *op_ASSIGN_68 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_66)); // seq(h_tmp134; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j)) ...; - RzILOpEffect *seq_69 = SEQN(2, op_ASSIGN_67, EMPTY()); + RzILOpEffect *seq_70 = SEQN(2, op_ASSIGN_68, EMPTY()); // seq(seq(h_tmp134; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ...; - RzILOpEffect *seq_70 = SEQN(2, seq_69, seq_46); + RzILOpEffect *seq_71 = SEQN(2, seq_70, seq_47); // while ((j <= 0x7)) { seq(seq(h_tmp134; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << ... }; - RzILOpPure *op_LE_42 = SLE(VARL("j"), SN(32, 7)); - RzILOpEffect *for_71 = REPEAT(op_LE_42, seq_70); + RzILOpPure *op_LE_43 = SLE(VARL("j"), SN(32, 7)); + RzILOpEffect *for_72 = REPEAT(op_LE_43, seq_71); // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp134; Pd = ((st8) ...; - RzILOpEffect *seq_72 = SEQN(2, op_ASSIGN_40, for_71); + RzILOpEffect *seq_73 = SEQN(2, op_ASSIGN_41, for_72); - RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, seq_72, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_25, seq_38, EMPTY(), seq_73, EMPTY()); return instruction_sequence; } @@ -2695,7 +2695,7 @@ RzILOpEffect *hex_il_op_a4_vcmpwgtui(HexInsnPktBundle *bundle) { // seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp138; Pd = ((st8) ...; RzILOpEffect *seq_72 = SEQN(2, op_ASSIGN_40, for_71); - RzILOpEffect *instruction_sequence = SEQN(3, imm_assign_25, seq_38, seq_72); + RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, seq_72, EMPTY()); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c index 7d299f1caed..b4cc5cea93f 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c index f713db8ad60..c02f3e9eb8d 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c index 04af8a681a5..c51f611b603 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c index 9cc81244737..53623523259 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c index 0de22d4f58c..fbfcfa6b419 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c index 39a7f0d06b2..f2949b32f8d 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c index 2e956539b7c..a77c73e1776 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c index 09a71beae7b..f307cc383ac 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_IMPORTED_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c index efc8505aa79..ca52c9e779e 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c index b0b47c5bf92..e109e242c4e 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_J4_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c index e5f7c58e847..586ddc8853d 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L2_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 15:00:15-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -78,7 +78,7 @@ RzILOpEffect *hex_il_op_l2_loadalignb_io(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_19 = LOGOR(op_RSHIFT_16, op_LSHIFT_18); RzILOpEffect *op_ASSIGN_21 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_19)); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, op_ASSIGN_21, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, op_ASSIGN_21); return instruction_sequence; } @@ -252,7 +252,7 @@ RzILOpEffect *hex_il_op_l2_loadalignb_pi(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_21 = LOGOR(op_RSHIFT_18, op_LSHIFT_20); RzILOpEffect *op_ASSIGN_23 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_21)); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23, EMPTY()); return instruction_sequence; } @@ -287,7 +287,7 @@ RzILOpEffect *hex_il_op_l2_loadalignb_pr(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_20 = LOGOR(op_RSHIFT_17, op_LSHIFT_19); RzILOpEffect *op_ASSIGN_22 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_20)); - RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22); + RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22, EMPTY()); return instruction_sequence; } @@ -368,7 +368,7 @@ RzILOpEffect *hex_il_op_l2_loadalignh_pbr(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_24 = LOGOR(op_RSHIFT_21, op_LSHIFT_23); RzILOpEffect *op_ASSIGN_26 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_24)); - RzILOpEffect *instruction_sequence = SEQN(5, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, op_ASSIGN_26); + RzILOpEffect *instruction_sequence = SEQN(6, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, op_ASSIGN_26, EMPTY()); return instruction_sequence; } @@ -495,7 +495,7 @@ RzILOpEffect *hex_il_op_l2_loadalignh_pi(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_21 = LOGOR(op_RSHIFT_18, op_LSHIFT_20); RzILOpEffect *op_ASSIGN_23 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_21)); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, op_ASSIGN_23, EMPTY()); return instruction_sequence; } @@ -530,7 +530,7 @@ RzILOpEffect *hex_il_op_l2_loadalignh_pr(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_20 = LOGOR(op_RSHIFT_17, op_LSHIFT_19); RzILOpEffect *op_ASSIGN_22 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_20)); - RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22); + RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, op_ASSIGN_22, EMPTY()); return instruction_sequence; } @@ -754,7 +754,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw2_pci(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp174; Rd = ((st32) ...; RzILOpEffect *seq_57 = SEQN(2, op_ASSIGN_20, for_56); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_57); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_57, EMPTY()); return instruction_sequence; } @@ -833,7 +833,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw2_pcr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp176; Rd = ((st32) ...; RzILOpEffect *seq_75 = SEQN(2, op_ASSIGN_38, for_74); - RzILOpEffect *instruction_sequence = SEQN(6, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_75); + RzILOpEffect *instruction_sequence = SEQN(7, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_75, EMPTY()); return instruction_sequence; } @@ -903,7 +903,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw2_pi(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp177; Rd = ((st32) ...; RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_16, for_52); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, seq_53); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, seq_53, EMPTY()); return instruction_sequence; } @@ -971,7 +971,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw2_pr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp178; Rd = ((st32) ...; RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_15, for_51); - RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, seq_52); + RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, seq_52, EMPTY()); return instruction_sequence; } @@ -1038,7 +1038,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw4_io(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp179; Rdd = ((st64) ...; RzILOpEffect *seq_50 = SEQN(2, op_ASSIGN_14, for_49); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, seq_50, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, seq_50); return instruction_sequence; } @@ -1195,7 +1195,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw4_pci(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp183; Rdd = ((st64) ...; RzILOpEffect *seq_56 = SEQN(2, op_ASSIGN_20, for_55); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56); + RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56, EMPTY()); return instruction_sequence; } @@ -1274,7 +1274,7 @@ RzILOpEffect *hex_il_op_l2_loadbsw4_pcr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp185; Rdd = ((st64) ...; RzILOpEffect *seq_74 = SEQN(2, op_ASSIGN_38, for_73); - RzILOpEffect *instruction_sequence = SEQN(7, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_74, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_74); return instruction_sequence; } @@ -1559,7 +1559,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw2_pbr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp190; Rd = ((st32) ...; RzILOpEffect *seq_56 = SEQN(2, op_ASSIGN_19, for_55); - RzILOpEffect *instruction_sequence = SEQN(5, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_56); + RzILOpEffect *instruction_sequence = SEQN(6, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_56, EMPTY()); return instruction_sequence; } @@ -1785,7 +1785,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw2_pi(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp195; Rd = ((st32) ...; RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_16, for_52); - RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, seq_53, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, op_ASSIGN_3, EMPTY(), op_ASSIGN_8, EMPTY(), op_ASSIGN_14, seq_53); return instruction_sequence; } @@ -1853,7 +1853,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw2_pr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp196; Rd = ((st32) ...; RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_15, for_51); - RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, seq_52, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, EMPTY(), op_ASSIGN_7, EMPTY(), op_ASSIGN_13, seq_52); return instruction_sequence; } @@ -1920,7 +1920,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw4_io(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp197; Rdd = ((st64) ...; RzILOpEffect *seq_50 = SEQN(2, op_ASSIGN_14, for_49); - RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, seq_50); + RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_6, EMPTY(), op_ASSIGN_12, seq_50, EMPTY()); return instruction_sequence; } @@ -2000,7 +2000,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw4_pbr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp199; Rdd = ((st64) ...; RzILOpEffect *seq_55 = SEQN(2, op_ASSIGN_19, for_54); - RzILOpEffect *instruction_sequence = SEQN(6, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_55, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(5, seq_8, op_ASSIGN_11, EMPTY(), op_ASSIGN_17, seq_55); return instruction_sequence; } @@ -2077,7 +2077,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw4_pci(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp201; Rdd = ((st64) ...; RzILOpEffect *seq_56 = SEQN(2, op_ASSIGN_20, for_55); - RzILOpEffect *instruction_sequence = SEQN(8, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_5, seq_12, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_18, seq_56); return instruction_sequence; } @@ -2156,7 +2156,7 @@ RzILOpEffect *hex_il_op_l2_loadbzw4_pcr(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp203; Rdd = ((st64) ...; RzILOpEffect *seq_74 = SEQN(2, op_ASSIGN_38, for_73); - RzILOpEffect *instruction_sequence = SEQN(7, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_74, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, seq_30, op_ASSIGN_3, EMPTY(), EMPTY(), op_ASSIGN_36, seq_74); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c index 84f06053601..f8cdfdcd620 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L4_ops.c @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 15:00:15-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -706,9 +706,9 @@ RzILOpEffect *hex_il_op_l4_loadalignb_ap(HexInsnPktBundle *bundle) { RzILOpEffect *op_ASSIGN_18 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_16)); // Re = ((st32) U); - RzILOpEffect *op_ASSIGN_22 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); + RzILOpEffect *op_ASSIGN_21 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, op_ASSIGN_18, EMPTY(), op_ASSIGN_22); + RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, op_ASSIGN_18, op_ASSIGN_21); return instruction_sequence; } @@ -747,7 +747,7 @@ RzILOpEffect *hex_il_op_l4_loadalignb_ur(HexInsnPktBundle *bundle) { RzILOpPure *op_OR_22 = LOGOR(op_RSHIFT_19, op_LSHIFT_21); RzILOpEffect *op_ASSIGN_24 = WRITE_REG(bundle, Ryy_op, CAST(64, IL_FALSE, op_OR_22)); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, op_ASSIGN_24); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, op_ASSIGN_24, EMPTY()); return instruction_sequence; } @@ -887,9 +887,9 @@ RzILOpEffect *hex_il_op_l4_loadbsw2_ap(HexInsnPktBundle *bundle) { RzILOpEffect *seq_48 = SEQN(2, op_ASSIGN_11, for_47); // Re = ((st32) U); - RzILOpEffect *op_ASSIGN_52 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); + RzILOpEffect *op_ASSIGN_51 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_48, EMPTY(), op_ASSIGN_52); + RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_48, op_ASSIGN_51); return instruction_sequence; } @@ -961,7 +961,7 @@ RzILOpEffect *hex_il_op_l4_loadbsw2_ur(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x2)) { seq(seq(h_tmp225; Rd = ((st32) ...; RzILOpEffect *seq_54 = SEQN(2, op_ASSIGN_17, for_53); - RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_54, EMPTY()); + RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_54); return instruction_sequence; } @@ -1101,7 +1101,7 @@ RzILOpEffect *hex_il_op_l4_loadbsw4_ur(HexInsnPktBundle *bundle) { // seq(i = 0x0; while ((i < 0x4)) { seq(seq(h_tmp227; Rdd = ((st64) ...; RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_17, for_52); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_53); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, imm_assign_4, op_ASSIGN_9, EMPTY(), op_ASSIGN_15, seq_53, EMPTY()); return instruction_sequence; } @@ -1167,9 +1167,9 @@ RzILOpEffect *hex_il_op_l4_loadbzw2_ap(HexInsnPktBundle *bundle) { RzILOpEffect *seq_48 = SEQN(2, op_ASSIGN_11, for_47); // Re = ((st32) U); - RzILOpEffect *op_ASSIGN_51 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); + RzILOpEffect *op_ASSIGN_52 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_48, op_ASSIGN_51); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_48, EMPTY(), op_ASSIGN_52); return instruction_sequence; } @@ -1307,9 +1307,9 @@ RzILOpEffect *hex_il_op_l4_loadbzw4_ap(HexInsnPktBundle *bundle) { RzILOpEffect *seq_47 = SEQN(2, op_ASSIGN_11, for_46); // Re = ((st32) U); - RzILOpEffect *op_ASSIGN_50 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); + RzILOpEffect *op_ASSIGN_51 = WRITE_REG(bundle, Re_op, CAST(32, IL_FALSE, VARL("U"))); - RzILOpEffect *instruction_sequence = SEQN(6, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_47, op_ASSIGN_50); + RzILOpEffect *instruction_sequence = SEQN(7, imm_assign_0, op_ASSIGN_3, EMPTY(), op_ASSIGN_9, seq_47, EMPTY(), op_ASSIGN_51); return instruction_sequence; } diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c index 876ddb9c5c4..c4ca2d32486 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_L6_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c index 1ca840aef75..31df93c966c 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c index bcb3aa10fd6..bf3fc2b5855 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M4_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c index 01ab0600f16..151b1bfa53b 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M5_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c index 0d316bb0a5a..68595581f19 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M6_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c index 1e012e01484..0f0a149c801 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_M7_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c index 5bceef94202..7398c53de8f 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_R6_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c index 7e7bb8156c0..312f6647a58 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c index 5a29260871d..a946ef2620f 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S4_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c index f46235bd986..4f1a272db16 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S5_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c index 0a76311af73..541205cc1bc 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_S6_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c index 3bedcfb2694..240aee2a3eb 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SA1_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c index d0a6046d157..491c0bf559f 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL1_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c index 0bfe3155d23..8ae27e4b5c4 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SL2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c index 37360e326fd..64370195b82 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS1_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c index a40793fcde6..d1a4fbbc821 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_SS2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c index 7dbf8c00521..221cecc3016 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_UNDOCUMENTED_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c index a64fa65e939..d94e47bc265 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_V6_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c index 38df8918a46..b16773a2fd5 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y2_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c index c98c52f12a5..25889174f45 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y4_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c index 1ae34885edd..1abb6202005 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y5_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c index c1d94d02a6b..6fcaa8098e0 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_Y6_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c index bd901ddf779..b209b2fc51b 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_dep_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c index 498bccaf4f6..5523f3eaa1a 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_invalid_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c b/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c index e33cd0ac1ec..d455fe1a4b6 100644 --- a/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c +++ b/librz/analysis/arch/hexagon/il_ops/hexagon_il_non_insn_ops.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/analysis/hexagon_dwarf_reg_num_table.inc b/librz/analysis/hexagon_dwarf_reg_num_table.inc index 89eef05a504..a833bf997b4 100644 --- a/librz/analysis/hexagon_dwarf_reg_num_table.inc +++ b/librz/analysis/hexagon_dwarf_reg_num_table.inc @@ -3,7 +3,7 @@ // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) -// Date of code generation: 2023-11-17 15:27:57-05:00 +// Date of code generation: 2023-11-21 15:00:15-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: diff --git a/librz/analysis/p/analysis_hexagon.c b/librz/analysis/p/analysis_hexagon.c index 355b9f0c73a..0756cfa0c1a 100644 --- a/librz/analysis/p/analysis_hexagon.c +++ b/librz/analysis/p/analysis_hexagon.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/arch/hexagon/hexagon.c b/librz/asm/arch/hexagon/hexagon.c index d14b3eec799..24d57956f9f 100644 --- a/librz/asm/arch/hexagon/hexagon.c +++ b/librz/asm/arch/hexagon/hexagon.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/arch/hexagon/hexagon.h b/librz/asm/arch/hexagon/hexagon.h index c836d5b4a53..7ee2e7cc0b4 100644 --- a/librz/asm/arch/hexagon/hexagon.h +++ b/librz/asm/arch/hexagon/hexagon.h @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/arch/hexagon/hexagon_arch.c b/librz/asm/arch/hexagon/hexagon_arch.c index 8a5ab077efb..08bf31fa90e 100644 --- a/librz/asm/arch/hexagon/hexagon_arch.c +++ b/librz/asm/arch/hexagon/hexagon_arch.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/arch/hexagon/hexagon_arch.h b/librz/asm/arch/hexagon/hexagon_arch.h index d809d4562e8..697009c96ad 100644 --- a/librz/asm/arch/hexagon/hexagon_arch.h +++ b/librz/asm/arch/hexagon/hexagon_arch.h @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/arch/hexagon/hexagon_disas.c b/librz/asm/arch/hexagon/hexagon_disas.c index 7aa93086c0b..3caa5ea8ce2 100644 --- a/librz/asm/arch/hexagon/hexagon_disas.c +++ b/librz/asm/arch/hexagon/hexagon_disas.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/arch/hexagon/hexagon_insn.h b/librz/asm/arch/hexagon/hexagon_insn.h index 0542925df21..813b856980a 100644 --- a/librz/asm/arch/hexagon/hexagon_insn.h +++ b/librz/asm/arch/hexagon/hexagon_insn.h @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/arch/hexagon/hexagon_reg_tables.h b/librz/asm/arch/hexagon/hexagon_reg_tables.h index 3b4fe22457c..dfa52255a15 100644 --- a/librz/asm/arch/hexagon/hexagon_reg_tables.h +++ b/librz/asm/arch/hexagon/hexagon_reg_tables.h @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00 diff --git a/librz/asm/p/asm_hexagon.c b/librz/asm/p/asm_hexagon.c index cae957b295d..4f000453342 100644 --- a/librz/asm/p/asm_hexagon.c +++ b/librz/asm/p/asm_hexagon.c @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-21 15:00:15-05:00 +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) // Date of code generation: 2023-11-17 15:27:57-05:00