From 41e700bbcd5e0d86ca16f472b3d4ea221a5e30f2 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Mon, 20 Nov 2023 04:52:43 +0000 Subject: [PATCH] Fix FNEQ: x and y were interchanged. (#3973) * Fix FNEQ: x and y were interchanged. * Add macros for LT, LE, GT, GE * Add a test for NaN. --- librz/include/rz_il/rz_il_opbuilder_begin.h | 8 ++++++-- librz/include/rz_il/rz_il_opbuilder_end.h | 4 ++++ test/db/asm/arm_32 | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/librz/include/rz_il/rz_il_opbuilder_begin.h b/librz/include/rz_il/rz_il_opbuilder_begin.h index b414260998d..211d9995b6e 100644 --- a/librz/include/rz_il/rz_il_opbuilder_begin.h +++ b/librz/include/rz_il/rz_il_opbuilder_begin.h @@ -98,8 +98,12 @@ #define AND(x, y) rz_il_op_new_bool_and(x, y) #define OR(x, y) rz_il_op_new_bool_or(x, y) -#define FNEQ(flx, fly) OR(FORDER(flx, fly), FORDER(DUP(flx), DUP(fly))) -#define FEQ(flx, fly) INV(FNEQ(flx, fly)) +#define FNEQ(flx, fly) OR(OR(IS_FNAN(flx), IS_FNAN(fly)), OR(FORDER(DUP(flx), DUP(fly)), FORDER(DUP(fly), DUP(flx)))) +#define FEQ(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), INV(FNEQ(DUP(flx), DUP(fly)))) +#define FLT(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), FORDER(DUP(flx), DUP(fly))) +#define FLE(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), OR(FLT(DUP(flx), DUP(fly)), FEQ(DUP(flx), DUP(fly)))) +#define FGT(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), INV(FLE(DUP(flx), DUP(fly)))) +#define FGE(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), INV(FLT(DUP(flx), DUP(fly)))) #define UNSIGNED(n, x) rz_il_op_new_unsigned(n, x) #define SIGNED(n, x) rz_il_op_new_signed(n, x) diff --git a/librz/include/rz_il/rz_il_opbuilder_end.h b/librz/include/rz_il/rz_il_opbuilder_end.h index 05ceb30591e..1b75018372b 100644 --- a/librz/include/rz_il/rz_il_opbuilder_end.h +++ b/librz/include/rz_il/rz_il_opbuilder_end.h @@ -56,6 +56,10 @@ #undef FMAD #undef FNEQ #undef FEQ +#undef FLT +#undef FLE +#undef FGE +#undef FGT #undef IL_FALSE #undef IL_TRUE diff --git a/test/db/asm/arm_32 b/test/db/asm/arm_32 index 3aec5cc31a9..250b25b3f6a 100644 --- a/test/db/asm/arm_32 +++ b/test/db/asm/arm_32 @@ -691,7 +691,7 @@ d "vacgt.f32 q0, q1, q2" 540e22f3 0x0 (seq empty (set d0 (cast 64 false (<< (cas d "vceq.i8 d0, d1, d2" 120801f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x0) false)) (cast 8 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x8) false)) (cast 8 false (>> (var d2) (bv 8 0x8) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x8) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x10) false)) (cast 8 false (>> (var d2) (bv 8 0x10) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x18) false)) (cast 8 false (>> (var d2) (bv 8 0x18) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x18) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x20) false)) (cast 8 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x28) false)) (cast 8 false (>> (var d2) (bv 8 0x28) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x28) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x30) false)) (cast 8 false (>> (var d2) (bv 8 0x30) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x30) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x38) false)) (cast 8 false (>> (var d2) (bv 8 0x38) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x38) false))) d "vceq.i16 d0, d1, d2" 120811f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x0) false)) (cast 16 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x10) false)) (cast 16 false (>> (var d2) (bv 8 0x10) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x20) false)) (cast 16 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x30) false)) (cast 16 false (>> (var d2) (bv 8 0x30) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x30) false))) d "vceq.i32 d0, d1, d2" 120821f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 32 false (>> (var d1) (bv 8 0x0) false)) (cast 32 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 32 false (>> (var d1) (bv 8 0x20) false)) (cast 32 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false))) -d "vceq.f32 d0, d1, d2" 020e01f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (! (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )) (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (! (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )) (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false))) +d "vceq.f32 d0, d1, d2" 020e01f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (&& (! (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )))) (! (|| (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) ))) (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )) (<. (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )))))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (&& (! (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )))) (! (|| (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) ))) (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )) (<. (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )))))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false))) d "vcge.s8 d0, d1, d2" 120301f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x0) false)) (cast 8 false (>> (var d2) (bv 8 0x0) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x0) false)) (cast 8 false (>> (var d2) (bv 8 0x0) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x8) false)) (cast 8 false (>> (var d2) (bv 8 0x8) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x8) false)) (cast 8 false (>> (var d2) (bv 8 0x8) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x8) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x10) false)) (cast 8 false (>> (var d2) (bv 8 0x10) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x10) false)) (cast 8 false (>> (var d2) (bv 8 0x10) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x18) false)) (cast 8 false (>> (var d2) (bv 8 0x18) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x18) false)) (cast 8 false (>> (var d2) (bv 8 0x18) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x18) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x20) false)) (cast 8 false (>> (var d2) (bv 8 0x20) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x20) false)) (cast 8 false (>> (var d2) (bv 8 0x20) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x28) false)) (cast 8 false (>> (var d2) (bv 8 0x28) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x28) false)) (cast 8 false (>> (var d2) (bv 8 0x28) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x28) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x30) false)) (cast 8 false (>> (var d2) (bv 8 0x30) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x30) false)) (cast 8 false (>> (var d2) (bv 8 0x30) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x30) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x38) false)) (cast 8 false (>> (var d2) (bv 8 0x38) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x38) false)) (cast 8 false (>> (var d2) (bv 8 0x38) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x38) false))) d "vcge.s16 d0, d1, d2" 120311f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x0) false)) (cast 16 false (>> (var d2) (bv 8 0x0) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x0) false)) (cast 16 false (>> (var d2) (bv 8 0x0) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x10) false)) (cast 16 false (>> (var d2) (bv 8 0x10) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x10) false)) (cast 16 false (>> (var d2) (bv 8 0x10) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x20) false)) (cast 16 false (>> (var d2) (bv 8 0x20) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x20) false)) (cast 16 false (>> (var d2) (bv 8 0x20) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x30) false)) (cast 16 false (>> (var d2) (bv 8 0x30) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x30) false)) (cast 16 false (>> (var d2) (bv 8 0x30) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x30) false))) d "vcge.s32 d0, d1, d2" 120321f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 32 false (>> (var d1) (bv 8 0x0) false)) (cast 32 false (>> (var d2) (bv 8 0x0) false)))) (== (cast 32 false (>> (var d1) (bv 8 0x0) false)) (cast 32 false (>> (var d2) (bv 8 0x0) false)))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 32 false (>> (var d1) (bv 8 0x20) false)) (cast 32 false (>> (var d2) (bv 8 0x20) false)))) (== (cast 32 false (>> (var d1) (bv 8 0x20) false)) (cast 32 false (>> (var d2) (bv 8 0x20) false)))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))