From 042f9174a4b5568975af7a4d387736c7f3452ab5 Mon Sep 17 00:00:00 2001 From: billow Date: Mon, 16 Dec 2024 22:03:55 +0800 Subject: [PATCH] fix xtensa asm tests --- test/db/asm/xtensa | 498 ++++++++++++++++++++++----------------------- 1 file changed, 249 insertions(+), 249 deletions(-) diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa index 8ab680a67a6..97bd946ad6d 100644 --- a/test/db/asm/xtensa +++ b/test/db/asm/xtensa @@ -1,137 +1,137 @@ -d "abs a1, a0" 001160 0x0 (set a1 (ite (! (sle (var a0) (bv 32 0x0))) (var a0) (~- (var a0)))) +d "abs a1, a0" 001160 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (~- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) d "abs.s f1, f2" 1012fa 0x0 (set f1 (cast 64 false (fbits (fpos (float 0 (var f2) ))))) -d "add a0, a0, a0" 000080 0x0 (set a0 (+ (var a0) (var a0))) +d "add a0, a0, a0" 000080 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "add.s f0, f0, f0" 00000a 0x0 (seq (set fres (+. rna (float 0 (var f0) ) (float 0 (var f0) ))) (set f0 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))))) -d "add.n a0, a0, a0" 0a00 0x0 (set a0 (+ (var a0) (var a0))) +d "add.n a0, a0, a0" 0a00 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "addexp.s f0, f1" e001fa 0x0 (seq (set FRr (| (& (var f0) (~ (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false) (bv 64 0x1f) false))) (& (<< (^ (& (>> (var f0) (bv 64 0x1f) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false)) (& (>> (var f1) (bv 64 0x1f) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false))) (bv 64 0x1f) false) (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false) (bv 64 0x1f) false)))) (set FRr (| (& (var FRr) (~ (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false) (bv 64 0x17) false))) (& (<< (- (+ (& (>> (var f0) (bv 64 0x17) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false)) (& (>> (var f1) (bv 64 0x17) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false))) (bv 64 0x7f)) (bv 64 0x17) false) (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false) (bv 64 0x17) false)))) (set f0 (var FRr))) d "addexpm.s f1, f2" f012fa 0x0 (seq (set FRr (| (& (var f1) (~ (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false) (bv 64 0x1f) false))) (& (<< (^ (& (>> (var f1) (bv 64 0x1f) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false)) (& (>> (var f2) (bv 64 0x16) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false))) (bv 64 0x1f) false) (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false) (bv 64 0x1f) false)))) (set FRr (| (& (var FRr) (~ (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false) (bv 64 0x17) false))) (& (<< (- (+ (& (>> (var f1) (bv 64 0x17) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false)) (& (>> (var f2) (bv 64 0xe) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false))) (bv 64 0x7f)) (bv 64 0x17) false) (<< (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false) (bv 64 0x17) false)))) (set f1 (var FRr))) -d "addi a3, a4, -1" 32c4ff 0x0 (set a3 (+ (var a4) (bv 32 0xffffffff))) -d "addi.n a2, a3, 1" 1b23 0x0 (set a2 (+ (var a3) (bv 32 0x1))) -d "addmi a3, a4, -0x100" 32d4ff 0x0 (set a3 (+ (var a4) (bv 32 0xffffff00))) -d "addx2 a2, a3, a1" 102390 0x0 (set a2 (+ (<< (var a3) (bv 32 0x1) false) (var a1))) -d "addx4 a2, a3, a1" 1023a0 0x0 (set a2 (+ (<< (var a3) (bv 32 0x2) false) (var a1))) -d "addx8 a2, a3, a1" 1023b0 0x0 (set a2 (+ (<< (var a3) (bv 32 0x3) false) (var a1))) +d "addi a3, a4, -1" 32c4ff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false)))) (bv 32 0xffffffff))) +d "addi.n a2, a3, 1" 1b23 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) +d "addmi a3, a4, -0x100" 32d4ff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false)))) (bv 32 0xffffff00))) +d "addx2 a2, a3, a1" 102390 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1) false) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "addx4 a2, a3, a1" 1023a0 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x2) false) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "addx8 a2, a3, a1" 1023b0 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3) false) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "all4 b1, b4" 109400 0x0 (set b1 (&& (&& (&& (var b4) (var b5)) (var b6)) (var b7))) d "all8 b1, b8" 10b800 0x0 (set b1 (&& (&& (&& (&& (&& (&& (&& (var b8) (var b9)) (var b10)) (var b11)) (var b12)) (var b13)) (var b14)) (var b15))) -d "and a2, a3, a1" 102310 0x0 (set a2 (& (var a3) (var a1))) +d "and a2, a3, a1" 102310 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (& (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "andb b2, b3, b1" 102302 0x0 (set b2 (&& (var b3) (var b1))) d "andbc b2, b3, b1" 102312 0x0 (set b2 (&& (var b3) (! (var b1)))) d "any4 b2, b4" 208400 0x0 (set b2 (|| (|| (|| (var b4) (var b5)) (var b6)) (var b7))) d "any8 b2, b8" 20a800 0x0 (set b2 (|| (|| (|| (|| (|| (|| (|| (var b8) (var b9)) (var b10)) (var b11)) (var b12)) (var b13)) (var b14)) (var b15))) -d "ball a2, a1, . +3" 1742ff 0x0 (branch (is_zero (& (~ (var a2)) (var a1))) (jmp (bv 32 0x3)) nop) -d "bany a2, a1, . +3" 1782ff 0x0 (branch (! (is_zero (& (var a2) (var a1)))) (jmp (bv 32 0x3)) nop) -d "ball a2, a1, . +3" 1742ff 0x40000 (branch (is_zero (& (~ (var a2)) (var a1))) (jmp (bv 32 0x40003)) nop) -d "bany a2, a1, . +3" 1782ff 0x40000 (branch (! (is_zero (& (var a2) (var a1)))) (jmp (bv 32 0x40003)) nop) -d "bbc a2, a1, . +3" 1752ff 0x0 (seq (set b (^ (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false)) (bv 32 0x0))) (branch (is_zero (& (>> (var a2) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x3)) nop)) -d "bbc a2, a1, . +3" 1752ff 0x40000 (seq (set b (^ (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false)) (bv 32 0x0))) (branch (is_zero (& (>> (var a2) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x40003)) nop)) -d "bbci a2, 1, . +3" 1762ff 0x0 (seq (set b (^ (bv 32 0x1) (bv 32 0x0))) (branch (is_zero (& (>> (var a2) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x3)) nop)) -d "bbci a2, 1, . +3" 1762ff 0x40000 (seq (set b (^ (bv 32 0x1) (bv 32 0x0))) (branch (is_zero (& (>> (var a2) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x40003)) nop)) -d "beq a3, a2, . +3" 2713ff 0x0 (branch (== (var a3) (var a2)) (jmp (bv 32 0x3)) nop) -d "beq a3, a2, . +3" 2713ff 0x40000 (branch (== (var a3) (var a2)) (jmp (bv 32 0x40003)) nop) -d "beqi a4, 3, . +3" 2634ff 0x0 (branch (== (var a4) (bv 32 0x3)) (jmp (bv 32 0x3)) nop) -d "beqi a4, 3, . +3" 2634ff 0x40000 (branch (== (var a4) (bv 32 0x3)) (jmp (bv 32 0x40003)) nop) -d "beqz a2, . +3" 16f2ff 0x0 (branch (== (var a2) (bv 32 0x0)) (jmp (bv 32 0x3)) nop) -d "beqz a2, . +3" 16f2ff 0x40000 (branch (== (var a2) (bv 32 0x0)) (jmp (bv 32 0x40003)) nop) +d "ball a2, a1, . +3" 1742ff 0x0 (branch (is_zero (& (~ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x3)) nop) +d "bany a2, a1, . +3" 1782ff 0x0 (branch (! (is_zero (& (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) (jmp (bv 32 0x3)) nop) +d "ball a2, a1, . +3" 1742ff 0x40000 (branch (is_zero (& (~ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x40003)) nop) +d "bany a2, a1, . +3" 1782ff 0x40000 (branch (! (is_zero (& (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) (jmp (bv 32 0x40003)) nop) +d "bbc a2, a1, . +3" 1752ff 0x0 (seq (set b (^ (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false)) (bv 32 0x0))) (branch (is_zero (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x3)) nop)) +d "bbc a2, a1, . +3" 1752ff 0x40000 (seq (set b (^ (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false)) (bv 32 0x0))) (branch (is_zero (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x40003)) nop)) +d "bbci a2, 1, . +3" 1762ff 0x0 (seq (set b (^ (bv 32 0x1) (bv 32 0x0))) (branch (is_zero (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x3)) nop)) +d "bbci a2, 1, . +3" 1762ff 0x40000 (seq (set b (^ (bv 32 0x1) (bv 32 0x0))) (branch (is_zero (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (jmp (bv 32 0x40003)) nop)) +d "beq a3, a2, . +3" 2713ff 0x0 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (jmp (bv 32 0x3)) nop) +d "beq a3, a2, . +3" 2713ff 0x40000 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (jmp (bv 32 0x40003)) nop) +d "beqi a4, 3, . +3" 2634ff 0x0 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false)))) (bv 32 0x3)) (jmp (bv 32 0x3)) nop) +d "beqi a4, 3, . +3" 2634ff 0x40000 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false)))) (bv 32 0x3)) (jmp (bv 32 0x40003)) nop) +d "beqz a2, . +3" 16f2ff 0x0 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (jmp (bv 32 0x3)) nop) +d "beqz a2, . +3" 16f2ff 0x40000 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (jmp (bv 32 0x40003)) nop) d "bf b1, . +3" 7601ff 0x0 (branch (var b1) (jmp (bv 32 0x3)) nop) d "bf b1, . +3" 7601ff 0x40000 (branch (var b1) (jmp (bv 32 0x40003)) nop) -d "bge a2, a1, . +3" 17a2ff 0x0 (branch (|| (! (sle (var a2) (var a1))) (== (var a2) (var a1))) (jmp (bv 32 0x3)) nop) -d "bge a2, a1, . +3" 17a2ff 0x40000 (branch (|| (! (sle (var a2) (var a1))) (== (var a2) (var a1))) (jmp (bv 32 0x40003)) nop) -d "bgei a2, 1, . +3" e612ff 0x0 (branch (|| (! (sle (var a2) (bv 32 0x1))) (== (var a2) (bv 32 0x1))) (jmp (bv 32 0x3)) nop) -d "bgei a2, 1, . +3" e612ff 0x40000 (branch (|| (! (sle (var a2) (bv 32 0x1))) (== (var a2) (bv 32 0x1))) (jmp (bv 32 0x40003)) nop) -d "bgeu a2, a1, . +3" 17b2ff 0x0 (branch (|| (! (ule (var a2) (var a1))) (== (var a2) (var a1))) (jmp (bv 32 0x3)) nop) -d "bgeu a2, a1, . +3" 17b2ff 0x40000 (branch (|| (! (ule (var a2) (var a1))) (== (var a2) (var a1))) (jmp (bv 32 0x40003)) nop) -d "bgeui a2, 0x10000, . +3" f612ff 0x0 (branch (|| (! (ule (var a2) (bv 32 0x10000))) (== (var a2) (bv 32 0x10000))) (jmp (bv 32 0x3)) nop) -d "bgeui a2, 0x10000, . +3" f612ff 0x40000 (branch (|| (! (ule (var a2) (bv 32 0x10000))) (== (var a2) (bv 32 0x10000))) (jmp (bv 32 0x40003)) nop) -d "bgez a1, . +3" d6f1ff 0x0 (branch (|| (! (sle (var a1) (bv 32 0x0))) (== (var a1) (bv 32 0x0))) (jmp (bv 32 0x3)) nop) -d "bgez a1, . +3" d6f1ff 0x40000 (branch (|| (! (sle (var a1) (bv 32 0x0))) (== (var a1) (bv 32 0x0))) (jmp (bv 32 0x40003)) nop) -d "bnall a2, a1, . +3" 17c2ff 0x0 (branch (! (is_zero (& (~ (var a2)) (var a1)))) (jmp (bv 32 0x3)) nop) -d "bnall a2, a1, . +3" 17c2ff 0x40000 (branch (! (is_zero (& (~ (var a2)) (var a1)))) (jmp (bv 32 0x40003)) nop) -d "bnone a2, a1, . +3" 1702ff 0x0 (branch (is_zero (& (var a2) (var a1))) (jmp (bv 32 0x3)) nop) -d "bnone a2, a1, . +3" 1702ff 0x40000 (branch (is_zero (& (var a2) (var a1))) (jmp (bv 32 0x40003)) nop) -d "call0 . 0" c5ffff 0x0 (seq (set a0 (bv 32 0x3)) (jmp (bv 32 0x0))) -d "call4 . 0" d5ffff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set a4 (bv 32 0x40000003)) (jmp (bv 32 0x0))) -d "call8 . 0" e5ffff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set a8 (bv 32 0x80000003)) (jmp (bv 32 0x0))) -d "call12 . 0" f5ffff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set a12 (bv 32 0xc0000003)) (jmp (bv 32 0x0))) -d "call0 . 0" c5ffff 0x40000 (seq (set a0 (bv 32 0x40003)) (jmp (bv 32 0x40000))) -d "call4 . 0" d5ffff 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set a4 (bv 32 0x40040003)) (jmp (bv 32 0x40000))) -d "call8 . 0" e5ffff 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set a8 (bv 32 0x80040003)) (jmp (bv 32 0x40000))) -d "call12 . 0" f5ffff 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set a12 (bv 32 0xc0040003)) (jmp (bv 32 0x40000))) -d "callx12 a1" f00100 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (var a1)) (set a12 (bv 32 0x60000003)) (jmp (var next))) -d "callx8 a1" e00100 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (var a1)) (set a8 (bv 32 0x40000003)) (jmp (var next))) -d "callx4 a1" d00100 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (var a1)) (set a4 (bv 32 0x20000003)) (jmp (var next))) -d "callx0 a1" c00100 0x0 (seq (set next (var a1)) (set a0 (bv 32 0x3)) (jmp (var next))) -d "callx12 a1" f00100 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x3) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (var a1)) (set a12 (bv 32 0x60040003)) (jmp (var next))) -d "callx8 a1" e00100 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x2) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (var a1)) (set a8 (bv 32 0x40040003)) (jmp (var next))) -d "callx4 a1" d00100 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (bv 32 0x0) (bv 32 0x0))) (! (== (bv 32 0x1) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (var a1)) (set a4 (bv 32 0x20040003)) (jmp (var next))) -d "callx0 a1" c00100 0x40000 (seq (set next (var a1)) (set a0 (bv 32 0x40003)) (jmp (var next))) -d "ceil.s a1, f2, 0xf" f012ba 0x0 (seq (set fres (*. rna (float 0 (var f2) ) (float 0 (bv 32 0x47000000) ))) (set a1 (fcast_int 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) -d "clamps a2, a3, 8" 102333 0x0 (seq (set low (float 0 (bv 32 0x43800000) )) (set high (float 0 (bv 32 0x437f0000) )) (set x (float 0 (var a3) )) (set a2 (fbits (ite (&& (! (|| (is_nan (var x)) (is_nan (var high)))) (<. (var high) (var x))) (var high) (ite (&& (! (|| (is_nan (var x)) (is_nan (var low)))) (<. (var x) (var low))) (var low) (var x)))))) +d "bge a2, a1, . +3" 17a2ff 0x0 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x3)) nop) +d "bge a2, a1, . +3" 17a2ff 0x40000 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x40003)) nop) +d "bgei a2, 1, . +3" e612ff 0x0 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) (jmp (bv 32 0x3)) nop) +d "bgei a2, 1, . +3" e612ff 0x40000 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) (jmp (bv 32 0x40003)) nop) +d "bgeu a2, a1, . +3" 17b2ff 0x0 (branch (|| (! (ule (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x3)) nop) +d "bgeu a2, a1, . +3" 17b2ff 0x40000 (branch (|| (! (ule (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x40003)) nop) +d "bgeui a2, 0x10000, . +3" f612ff 0x0 (branch (|| (! (ule (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10000))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10000))) (jmp (bv 32 0x3)) nop) +d "bgeui a2, 0x10000, . +3" f612ff 0x40000 (branch (|| (! (ule (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10000))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10000))) (jmp (bv 32 0x40003)) nop) +d "bgez a1, . +3" d6f1ff 0x0 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (jmp (bv 32 0x3)) nop) +d "bgez a1, . +3" d6f1ff 0x40000 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (jmp (bv 32 0x40003)) nop) +d "bnall a2, a1, . +3" 17c2ff 0x0 (branch (! (is_zero (& (~ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) (jmp (bv 32 0x3)) nop) +d "bnall a2, a1, . +3" 17c2ff 0x40000 (branch (! (is_zero (& (~ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) (jmp (bv 32 0x40003)) nop) +d "bnone a2, a1, . +3" 1702ff 0x0 (branch (is_zero (& (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x3)) nop) +d "bnone a2, a1, . +3" 1702ff 0x40000 (branch (is_zero (& (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (jmp (bv 32 0x40003)) nop) +d "call0 . 0" c5ffff 0x0 (seq (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (bv 32 0x3)) (jmp (bv 32 0x0))) +d "call4 . 0" d5ffff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (bv 32 0x40000003)) (jmp (bv 32 0x0))) +d "call8 . 0" e5ffff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (bv 32 0x80000003)) (jmp (bv 32 0x0))) +d "call12 . 0" f5ffff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (bv 32 0xc0000003)) (jmp (bv 32 0x0))) +d "call0 . 0" c5ffff 0x40000 (seq (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (bv 32 0x40003)) (jmp (bv 32 0x40000))) +d "call4 . 0" d5ffff 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (bv 32 0x40040003)) (jmp (bv 32 0x40000))) +d "call8 . 0" e5ffff 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (bv 32 0x80040003)) (jmp (bv 32 0x40000))) +d "call12 . 0" f5ffff 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (bv 32 0xc0040003)) (jmp (bv 32 0x40000))) +d "callx12 a1" f00100 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (bv 32 0x60000003)) (jmp (var next))) +d "callx8 a1" e00100 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (bv 32 0x40000003)) (jmp (var next))) +d "callx4 a1" d00100 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (bv 32 0x20000003)) (jmp (var next))) +d "callx0 a1" c00100 0x0 (seq (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (bv 32 0x3)) (jmp (var next))) +d "callx12 a1" f00100 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x3))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x3) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x3) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (bv 32 0x60040003)) (jmp (var next))) +d "callx8 a1" e00100 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x2))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x2) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x2) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (bv 32 0x40040003)) (jmp (var next))) +d "callx4 a1" d00100 0x40000 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (bv 32 0x0))) (! (is_zero (bv 32 0x1))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (bv 32 0x0) (bv 32 0x3)) (== (bv 32 0x1) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x40000)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (bv 32 0x1) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (bv 32 0x20040003)) (jmp (var next))) +d "callx0 a1" c00100 0x40000 (seq (set next (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (bv 32 0x40003)) (jmp (var next))) +d "ceil.s a1, f2, 0xf" f012ba 0x0 (seq (set fres (*. rna (float 0 (var f2) ) (float 0 (bv 32 0x47000000) ))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (fcast_int 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) +d "clamps a2, a3, 8" 102333 0x0 (seq (set low (float 0 (bv 32 0x43800000) )) (set high (float 0 (bv 32 0x437f0000) )) (set x (float 0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) )) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (fbits (ite (&& (! (|| (is_nan (var x)) (is_nan (var high)))) (<. (var high) (var x))) (var high) (ite (&& (! (|| (is_nan (var x)) (is_nan (var low)))) (<. (var x) (var low))) (var low) (var x)))))) d "const.s f4, 3" 3043fa 0x0 (set f4 (cast 64 false (fbits (float 0 (bv 32 0x3f000000) )))) d "div0.s f1, f2" 7012fa 0x0 (set f1 (cast 64 false (fbits (/. rna (float 0 (var f1) ) (float 0 (var f2) ))))) d "divn.s f2, f3, f1" 10237a 0x0 (seq (set fr (float 0 (var f2) )) (set fs (float 0 (var f3) )) (set ft (float 0 (var f1) )) (set fres (+. rna (var fr) (*. rna (var fs) (fneg (var ft))))) (set f2 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false))) (& (<< (ite (fexcept e_underflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false))))) d "dsync" 302000 0x0 nop -d "entry a1, 0x7ff8" 36f1ff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x0))) (! (== (bv 32 0x0) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x0)))) (bv 32 0x1) (ite (&& (|| (! (== (bv 32 0x0) (bv 32 0x0))) (|| (! (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x0))) (! (== (bv 32 0x0) (bv 32 0x0))))) (! (== (var windowstart) (bv 32 0x1)))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3)) (== (bv 32 0x0) (bv 32 0x3)))) (! (== (var windowstart) (bv 32 0x2)))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (branch (|| (! (ule (var a1) (bv 32 0x3))) (|| (is_zero (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (== (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)))) nop (seq (branch (&& (ule (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x10)) (! (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x10)))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xf)) (set a15 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xe)) (set a14 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xd)) (set a13 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xc)) (set a12 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xb)) (set a11 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xa)) (set a10 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x9)) (set a9 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x8)) (set a8 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x7)) (set a7 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x6)) (set a6 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x5)) (set a5 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x4)) (set a4 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3)) (set a3 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x2)) (set a2 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x1)) (set a1 (- (var a1) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x0)) (set a0 (- (var a1) (bv 32 0x7ff8))) nop)))))))))))))))) nop) (set windowbase (+ (var windowbase) (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)))) (set windowstart (bv 32 0x1))))) +d "entry a1, 0x7ff8" 36f1ff 0x0 (seq (set cwoe (ite (! (is_zero (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set n (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)))) (! (is_zero (bv 32 0x0))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x1) (ite (&& (|| (! (is_zero (bv 32 0x0))) (|| (! (is_zero (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)))) (! (is_zero (bv 32 0x0))))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x2) (ite (&& (|| (== (bv 32 0x0) (bv 32 0x3)) (|| (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3)) (== (bv 32 0x0) (bv 32 0x3)))) (! (is_zero (& (>> (var windowstart) (+ (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))))) (bv 32 0x3) (bv 32 0x0))))) (branch (&& (== (var cwoe) (bv 32 0x1)) (! (== (var n) (bv 32 0x0)))) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var windowbase) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set m (+ (var windowbase) (var n))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set windowbase (var m)) (set nextPC (ite (== (var windowstart) (bv 32 0x0)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x2) (bv 32 0x3))))) nop) (branch (|| (! (ule (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3))) (|| (is_zero (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (== (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)))) nop (seq (branch (&& (ule (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x10)) (! (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x10)))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xf)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xe)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xd)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xc)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x3)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xb)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0xa)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x9)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x8)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x2)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x7)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x6)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x5)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x4)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x1)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x2)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x1)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) (branch (== (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x0)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x7ff8))) nop)))))))))))))))) nop) (set windowbase (+ (var windowbase) (& (>> (var ps) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)))) (set windowstart (bv 32 0x1))))) d "esync" 202000 0x0 nop d "excw" 802000 0x0 nop -d "extui a2, a1, 0x13, 5" 102345 0x0 (set a2 (let at (var a1) (& (bv 32 0x3f) (let at1 (| (& (var at) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x1f) false))) (& (<< (bv 32 0x0) (bv 32 0x1f) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x1f) false))) (>> (var at1) (bv 32 0x13) false))))) +d "extui a2, a1, 0x13, 5" 102345 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (let at (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (& (bv 32 0x3f) (let at1 (| (& (var at) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x1f) false))) (& (<< (bv 32 0x0) (bv 32 0x1f) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x1f) false))) (>> (var at1) (bv 32 0x13) false))))) d "extw" d02000 0x0 nop -d "float.s f2, a3, 1" 1023ca 0x0 (seq (set fres (fcast_float ieee754-bin32 rna (div (var a3) (bv 32 0x0)))) (set f2 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) -d "floor.s a2, f3, 1" 1023aa 0x0 (seq (set fres (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))) (set a2 (fcast_sint 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) +d "float.s f2, a3, 1" 1023ca 0x0 (seq (set fres (fcast_float ieee754-bin32 rna (div (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)))) (set f2 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) +d "floor.s a2, f3, 1" 1023aa 0x0 (seq (set fres (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (fcast_sint 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) d "isync" 002000 0x0 nop -d "jx a1" a00100 0x0 (jmp (var a1)) +d "jx a1" a00100 0x0 (jmp (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) d "j . +3" c6ffff 0x0 (jmp (bv 32 0x3)) d "j . +3" c6ffff 0x40000 (jmp (bv 32 0x40003)) -d "l8ui a1, a3, 0xff" 1203ff 0x0 (set a1 (cast 32 false (load 0 (+ (var a3) (bv 32 0xff))))) -d "l16si a1, a3, 0x1fe" 1293ff 0x0 (set a1 (let mem16 (loadw 0 16 (+ (var a3) (bv 32 0x1fe))) (>> (cast 32 false (<< (cast 32 false (var mem16)) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x10)) (msb (cast 32 false (<< (cast 32 false (var mem16)) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)))))) -d "l16ui a1, a3, 0x1fe" 1213ff 0x0 (set a1 (let mem16 (loadw 0 16 (+ (var a3) (bv 32 0x1fe))) (cast 32 false (var mem16)))) -d "l32r a2, . -4" 21ffff 0x0 (set a2 (loadw 0 32 (bv 32 0xfffffffc))) -d "l32i.n a2, a2, 0x3c" 28f2 0x0 (set a2 (loadw 0 32 (+ (var a2) (bv 32 0x3c)))) -d "l32i a1, a3, 0x3fc" 1223ff 0x0 (set a1 (loadw 0 32 (+ (var a3) (bv 32 0x3fc)))) -d "l32e a1, a3, -0x38" 102309 0x0 (set a1 (loadw 0 32 (+ (var a3) (bv 32 0xffffffc8)))) -d "lddec m3, a2" 043290 0x0 (seq (set vAddr (- (var a2) (bv 32 0x4))) (set m3 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "ldinc m2, a1" 042180 0x0 (seq (set vAddr (+ (var a1) (bv 32 0x4))) (set m2 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "loop a1, . +0x103" 7681ff 0x0 (seq (set lcount (- (var a1) (bv 32 0x1))) (set lbeg (bv 32 0x3)) (set lend (bv 32 0x103))) -d "loopgtz a1, . +0x103" 76a1ff 0x0 (seq (set lcount (- (var a1) (bv 32 0x1))) (set lbeg (bv 32 0x3)) (set lend (bv 32 0x103)) (branch (sle (var a1) (bv 32 0x0)) (jmp (bv 32 0x103)) nop)) -d "loopnez a1, . +0x103" 7691ff 0x0 (seq (set lcount (- (var a1) (bv 32 0x1))) (set lbeg (bv 32 0x3)) (set lend (bv 32 0x103)) (branch (== (var a1) (bv 32 0x0)) (jmp (bv 32 0x103)) nop)) -d "lsi f1, a2, 0x3fc" 1302ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0x3fc))) (set memVal (loadw 0 32 (var vAddr))) (set f1 (cast 64 false (var memVal)))) -d "lsip f1, a2, 0x3fc" 1382ff 0x0 (seq (set vAddr (var a2)) (set memVal (loadw 0 32 (var vAddr))) (set f1 (cast 64 false (var memVal))) (set a2 (+ (var vAddr) (bv 32 0x3fc)))) -d "lsx f2, a3, a1" 102308 0x0 (seq (set vAddr (+ (var a3) (var a1))) (set memVal (loadw 0 32 (var vAddr))) (set f2 (cast 64 false (var memVal)))) -d "lsxp f2, a3, a1" 102318 0x0 (seq (set vAddr (var a3)) (set memVal (loadw 0 32 (var vAddr))) (set f2 (cast 64 false (var memVal))) (set a3 (+ (var vAddr) (var a1)))) +d "l8ui a1, a3, 0xff" 1203ff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (cast 32 false (load 0 (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0xff))))) +d "l16si a1, a3, 0x1fe" 1293ff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (let mem16 (loadw 0 16 (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1fe))) (>> (cast 32 false (<< (cast 32 false (var mem16)) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x10)) (msb (cast 32 false (<< (cast 32 false (var mem16)) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)))))) +d "l16ui a1, a3, 0x1fe" 1213ff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (let mem16 (loadw 0 16 (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1fe))) (cast 32 false (var mem16)))) +d "l32r a2, . -4" 21ffff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 0 32 (bv 32 0xfffffffc))) +d "l32i.n a2, a2, 0x3c" 28f2 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 0 32 (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3c)))) +d "l32i a1, a3, 0x3fc" 1223ff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 0 32 (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fc)))) +d "l32e a1, a3, -0x38" 102309 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 0 32 (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0xffffffc8)))) +d "lddec m3, a2" 043290 0x0 (seq (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m3 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "ldinc m2, a1" 042180 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m2 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "loop a1, . +0x103" 7681ff 0x0 (seq (set lcount (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) (set lbeg (bv 32 0x3)) (set lend (bv 32 0x103))) +d "loopgtz a1, . +0x103" 76a1ff 0x0 (seq (set lcount (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) (set lbeg (bv 32 0x3)) (set lend (bv 32 0x103)) (branch (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (jmp (bv 32 0x103)) nop)) +d "loopnez a1, . +0x103" 7691ff 0x0 (seq (set lcount (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1))) (set lbeg (bv 32 0x3)) (set lend (bv 32 0x103)) (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (jmp (bv 32 0x103)) nop)) +d "lsi f1, a2, 0x3fc" 1302ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fc))) (set memVal (loadw 0 32 (var vAddr))) (set f1 (cast 64 false (var memVal)))) +d "lsip f1, a2, 0x3fc" 1382ff 0x0 (seq (set vAddr (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (set memVal (loadw 0 32 (var vAddr))) (set f1 (cast 64 false (var memVal))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (var vAddr) (bv 32 0x3fc)))) +d "lsx f2, a3, a1" 102308 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set memVal (loadw 0 32 (var vAddr))) (set f2 (cast 64 false (var memVal)))) +d "lsxp f2, a3, a1" 102318 0x0 (seq (set vAddr (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (set memVal (loadw 0 32 (var vAddr))) (set f2 (cast 64 false (var memVal))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (var vAddr) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) d "maddn.s f2, f3, f1" 10236a 0x0 (seq (set fr (float 0 (var f2) )) (set fs (float 0 (var f3) )) (set ft (float 0 (var f1) )) (set fres (+. rna (var fr) (*. rna (var fs) (var ft)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false))) (& (<< (ite (fexcept e_underflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false)))) (set f2 (cast 64 false (fbits (var fres))))) d "madd.s f2, f3, f1" 10234a 0x0 (seq (set fr (float 0 (var f2) )) (set fs (float 0 (var f3) )) (set ft (float 0 (var f1) )) (set fres (+. rna (var fr) (*. rna (var fs) (var ft)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false))) (& (<< (ite (fexcept e_underflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false)))) (set f2 (cast 64 false (fbits (var fres))))) -d "max a2, a3, a1" 102353 0x0 (set a2 (ite (&& (sle (var a3) (var a1)) (! (== (var a3) (var a1)))) (var a1) (var a3))) -d "maxu a2, a3, a1" 102373 0x0 (set a2 (ite (&& (ule (var a3) (var a1)) (! (== (var a3) (var a1)))) (var a1) (var a3))) -d "min a2, a3, a1" 102343 0x0 (set a2 (ite (! (sle (var a3) (var a1))) (var a1) (var a3))) -d "minu a2, a3, a1" 102363 0x0 (set a2 (ite (! (ule (var a3) (var a1))) (var a1) (var a3))) +d "max a2, a3, a1" 102353 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (&& (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (! (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "maxu a2, a3, a1" 102373 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (&& (ule (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (! (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "min a2, a3, a1" 102343 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "minu a2, a3, a1" 102363 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (! (ule (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "memw" c02000 0x0 nop -d "moveqz a2, a3, a1" 102383 0x0 (branch (== (var a1) (bv 32 0x0)) (set a2 (var a3)) nop) -d "moveqz.s f2, f3, a1" 10238b 0x0 (branch (== (var a1) (bv 32 0x0)) (set f2 (var f3)) nop) -d "movf a2, a3, b1" 1023c3 0x0 (branch (! (var b1)) (set a2 (var a3)) nop) +d "moveqz a2, a3, a1" 102383 0x0 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) +d "moveqz.s f2, f3, a1" 10238b 0x0 (branch (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (set f2 (var f3)) nop) +d "movf a2, a3, b1" 1023c3 0x0 (branch (! (var b1)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) d "movf.s f2, f3, b1" 1023cb 0x0 (branch (! (var b1)) (set f2 (var f3)) nop) -d "movgez a2, a3, a1" 1023b3 0x0 (branch (|| (! (sle (var a1) (bv 32 0x0))) (== (var a1) (bv 32 0x0))) (set a2 (var a3)) nop) -d "movgez.s f2, f3, a1" 1023bb 0x0 (branch (|| (! (sle (var a1) (bv 32 0x0))) (== (var a1) (bv 32 0x0))) (set f2 (var f3)) nop) -d "movi a1, -1" 12afff 0x0 (set a1 (bv 32 0xffffffff)) -d "movi.n a1, 0x3f" 3cf1 0x0 (set a1 (bv 32 0x3f)) -d "movltz a2, a3, a1" 1023a3 0x0 (branch (&& (sle (var a1) (bv 32 0x0)) (! (== (var a1) (bv 32 0x0)))) (set a2 (var a3)) nop) -d "movltz.s f2, f3, a1" 1023ab 0x0 (branch (&& (sle (var a1) (bv 32 0x0)) (! (== (var a1) (bv 32 0x0)))) (set f2 (var f3)) nop) -d "movnez a2, a3, a1" 102393 0x0 (branch (! (== (var a1) (bv 32 0x0))) (set a2 (var a3)) nop) -d "movnez.s f2, f3, a1" 10239b 0x0 (branch (! (== (var a1) (bv 32 0x0))) (set f2 (var f3)) nop) -d "movsp a1, a2" 101200 0x0 (branch (== (var windowstart) (bv 32 0x3)) nop (set a1 (var a2))) -d "movt a2, a3, b1" 1023d3 0x0 (branch (var b1) (set a2 (var a3)) nop) +d "movgez a2, a3, a1" 1023b3 0x0 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) +d "movgez.s f2, f3, a1" 1023bb 0x0 (branch (|| (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (set f2 (var f3)) nop) +d "movi a1, -1" 12afff 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (bv 32 0xffffffff)) +d "movi.n a1, 0x3f" 3cf1 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (bv 32 0x3f)) +d "movltz a2, a3, a1" 1023a3 0x0 (branch (&& (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (! (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) +d "movltz.s f2, f3, a1" 1023ab 0x0 (branch (&& (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)) (! (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)))) (set f2 (var f3)) nop) +d "movnez a2, a3, a1" 102393 0x0 (branch (! (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) +d "movnez.s f2, f3, a1" 10239b 0x0 (branch (! (== (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (set f2 (var f3)) nop) +d "movsp a1, a2" 101200 0x0 (branch (== (& (>> (var windowstart) (- (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x3)) false)) (bv 32 0x3)) nop (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "movt a2, a3, b1" 1023d3 0x0 (branch (var b1) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) d "movt.s f2, f3, b1" 1023db 0x0 (branch (var b1) (set f2 (var f3)) nop) d "msub.s f2, f3, f1" 10235a 0x0 (seq (set fr (float 0 (var f2) )) (set fs (float 0 (var f3) )) (set ft (float 0 (var f1) )) (set fres (-. rna (var fr) (*. rna (var fs) (var ft)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false))) (& (<< (ite (fexcept e_underflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false)))) (set f2 (cast 64 false (fbits (var fres))))) -d "mul.aa.ll a2, a1" 140274 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.aa.hl a2, a1" 140275 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.aa.lh a2, a1" 140276 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.aa.hh a2, a1" 140277 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.ll a2, m3" 440234 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.hl a2, m3" 440235 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.lh a2, m3" 440236 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.hh a2, m3" 440237 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.ll a2, m2" 040234 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.hl a2, m2" 040235 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.lh a2, m2" 040236 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mul.ad.hh a2, m2" 040237 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.aa.ll a2, a1" 140274 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.aa.hl a2, a1" 140275 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.aa.lh a2, a1" 140276 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.aa.hh a2, a1" 140277 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.ll a2, m3" 440234 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.hl a2, m3" 440235 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.lh a2, m3" 440236 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.hh a2, m3" 440237 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.ll a2, m2" 040234 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.hl a2, m2" 040235 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.lh a2, m2" 040236 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul.ad.hh a2, m2" 040237 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mul.dd.ll m0, m2" 040024 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mul.dd.hl m0, m2" 040025 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mul.dd.lh m0, m2" 040026 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) @@ -141,183 +141,183 @@ d "mul.dd.hl m1, m3" 444025 0x0 (seq (set m1 (& (>> (var m1) (bv 32 0x10) false) d "mul.dd.lh m1, m3" 444026 0x0 (seq (set m1 (& (>> (var m1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mul.dd.hh m1, m3" 444027 0x0 (seq (set m1 (& (>> (var m1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m3) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (* (var sm1) (var sm2))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mul.s f2, f3, f1" 10232a 0x0 (seq (set frs (float 0 (var f3) )) (set frt (float 0 (var f1) )) (set fres (*. rna (var frs) (var frt))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false))) (& (<< (ite (fexcept e_underflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x8) false)))) (set f2 (cast 64 false (fbits (var fres))))) -d "mul16u a2, a3, a1" 1023c1 0x0 (seq (set ars (& (>> (var a3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set art (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set a2 (* (var ars) (var art)))) -d "mul16s a2, a3, a1" 1023d1 0x0 (seq (set ars (>> (cast 32 false (<< (var a3) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x10)) (msb (cast 32 false (<< (var a3) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false))))) (set art (>> (cast 32 false (<< (var a1) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x10)) (msb (cast 32 false (<< (var a1) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false))))) (set a2 (* (var ars) (var art)))) -d "mula.aa.ll a2, a1" 140278 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.aa.hl a2, a1" 140279 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.aa.lh a2, a1" 14027a 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.aa.hh a2, a1" 14027b 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.ad.ll a0, m2" 040038 0x0 (seq (set m1 (& (>> (var a0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.ad.hl a0, m2" 040039 0x0 (seq (set m1 (& (>> (var a0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.ad.lh a0, m2" 04003a 0x0 (seq (set m1 (& (>> (var a0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.ad.hh a0, m2" 04003b 0x0 (seq (set m1 (& (>> (var a0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.da.ll m0, a1" 140068 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.da.hl m0, a1" 140069 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.da.lh m0, a1" 14006a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.da.hh m0, a1" 14006b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mul16u a2, a3, a1" 1023c1 0x0 (seq (set ars (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set art (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (* (var ars) (var art)))) +d "mul16s a2, a3, a1" 1023d1 0x0 (seq (set ars (>> (cast 32 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x10)) (msb (cast 32 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false))))) (set art (>> (cast 32 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x10)) (msb (cast 32 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x20) (bv 32 0x10)) (bv 32 0x0)) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (* (var ars) (var art)))) +d "mula.aa.ll a2, a1" 140278 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.aa.hl a2, a1" 140279 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.aa.lh a2, a1" 14027a 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.aa.hh a2, a1" 14027b 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.ad.ll a0, m2" 040038 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.ad.hl a0, m2" 040039 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.ad.lh a0, m2" 04003a 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.ad.hh a0, m2" 04003b 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.da.ll m0, a1" 140068 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.da.hl m0, a1" 140069 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.da.lh m0, a1" 14006a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.da.hh m0, a1" 14006b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mula.dd.ll m0, m2" 040028 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mula.dd.hl m0, m2" 040029 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mula.dd.lh m0, m2" 04002a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "mula.dd.hh m0, m2" 04002b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mula.da.ll.lddec m0, a2, m0, a1" 140258 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.da.hl.lddec m0, a2, m0, a1" 140259 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.da.lh.lddec m0, a2, m0, a1" 14025a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.da.hh.lddec m0, a2, m0, a1" 14025b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.da.ll.ldinc m0, a2, m0, a1" 140248 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.da.hl.ldinc m0, a2, m0, a1" 140249 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.da.lh.ldinc m0, a2, m0, a1" 14024a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.da.hh.ldinc m0, a2, m0, a1" 14024b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr))) -d "mula.dd.ll.lddec m0, a1, m0, m2" 040118 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mula.dd.hl.lddec m0, a1, m0, m2" 040119 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mula.dd.lh.lddec m0, a1, m0, m2" 04011a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mula.dd.hh.lddec m0, a1, m0, m2" 04011b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mula.dd.ll.ldinc m0, a1, m0, m2" 040108 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mula.dd.hl.ldinc m0, a1, m0, m2" 040109 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mula.dd.lh.ldinc m0, a1, m0, m2" 04010a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mula.dd.hh.ldinc m0, a1, m0, m2" 04010b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr))) -d "mull a2, a3, a1" 102382 0x0 (seq (set ars (cast 64 false (var a3))) (set art (cast 64 false (var a1))) (set a2 (cast 32 false (* (var ars) (var art))))) -d "muls.aa.ll a2, a1" 14027c 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.aa.hl a2, a1" 14027d 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.aa.lh a2, a1" 14027e 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.aa.hh a2, a1" 14027f 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.ad.ll a2, m2" 04023c 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.ad.hl a2, m2" 04023d 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.ad.lh a2, m2" 04023e 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.ad.hh a2, m2" 04023f 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.da.ll m0, a1" 14006c 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.da.hl m0, a1" 14006d 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.da.lh m0, a1" 14006e 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "muls.da.hh m0, a1" 14006f 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "mula.da.ll.lddec m0, a2, m0, a1" 140258 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.da.hl.lddec m0, a2, m0, a1" 140259 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.da.lh.lddec m0, a2, m0, a1" 14025a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.da.hh.lddec m0, a2, m0, a1" 14025b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.da.ll.ldinc m0, a2, m0, a1" 140248 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.da.hl.ldinc m0, a2, m0, a1" 140249 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.da.lh.ldinc m0, a2, m0, a1" 14024a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.da.hh.ldinc m0, a2, m0, a1" 14024b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.ll.lddec m0, a1, m0, m2" 040118 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.hl.lddec m0, a1, m0, m2" 040119 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.lh.lddec m0, a1, m0, m2" 04011a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.hh.lddec m0, a1, m0, m2" 04011b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.ll.ldinc m0, a1, m0, m2" 040108 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.hl.ldinc m0, a1, m0, m2" 040109 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.lh.ldinc m0, a1, m0, m2" 04010a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mula.dd.hh.ldinc m0, a1, m0, m2" 04010b 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var vAddr))) +d "mull a2, a3, a1" 102382 0x0 (seq (set ars (cast 64 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set art (cast 64 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (cast 32 false (* (var ars) (var art))))) +d "muls.aa.ll a2, a1" 14027c 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.aa.hl a2, a1" 14027d 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.aa.lh a2, a1" 14027e 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.aa.hh a2, a1" 14027f 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.ad.ll a2, m2" 04023c 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.ad.hl a2, m2" 04023d 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.ad.lh a2, m2" 04023e 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.ad.hh a2, m2" 04023f 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.da.ll m0, a1" 14006c 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.da.hl m0, a1" 14006d 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.da.lh m0, a1" 14006e 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "muls.da.hh m0, a1" 14006f 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "muls.dd.ll m0, m2" 04002c 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "muls.dd.hl m0, m2" 04002d 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "muls.dd.lh m0, m2" 04002e 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) d "muls.dd.hh m0, m2" 04002f 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var m2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (- (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "mulsh a2, a3, a1" 1023b2 0x0 (seq (set ars (>> (cast 64 false (<< (var a3) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x20)) (msb (cast 64 false (<< (var a3) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false))))) (set art (>> (cast 64 false (<< (var a1) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x20)) (msb (cast 64 false (<< (var a1) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false))))) (set tp (* (var ars) (var art))) (set a2 (cast 32 false (>> (var tp) (bv 32 0x20) false)))) -d "muluh a2, a3, a1" 1023a2 0x0 (seq (set ars (cast 64 false (var a3))) (set art (cast 64 false (var a1))) (set tp (* (var ars) (var art))) (set a2 (cast 32 false (>> (var tp) (bv 32 0x20) false)))) -d "neg a2, a1" 102060 0x0 (set a2 (~- (var a1))) +d "mulsh a2, a3, a1" 1023b2 0x0 (seq (set ars (>> (cast 64 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x20)) (msb (cast 64 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false))))) (set art (>> (cast 64 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x20)) (msb (cast 64 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x40) (bv 32 0x20)) (bv 32 0x0)) false))))) (set tp (* (var ars) (var art))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (cast 32 false (>> (var tp) (bv 32 0x20) false)))) +d "muluh a2, a3, a1" 1023a2 0x0 (seq (set ars (cast 64 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set art (cast 64 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set tp (* (var ars) (var art))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (cast 32 false (>> (var tp) (bv 32 0x20) false)))) +d "neg a2, a1" 102060 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (~- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "neg.s f1, f2" 6012fa 0x0 (set f1 (cast 64 false (fbits (fneg (float 0 (var f2) ))))) d "nexp01.s f1, f2" b012fa 0x0 (seq (set rs (var f2)) (set frs (float 0 (var rs) )) (set frs64 (fconvert ieee754-bin64 rna (var frs))) (set rs31 (<< (ite (! (ite (== (& (>> (var rs) (bv 32 0x1f) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false)) (bv 64 0x0)) false true)) (bv 64 0x1) (bv 64 0x0)) (bv 32 0x1f) false)) (set f1 (ite (== (& (>> (var rs) (bv 32 0x17) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false)) (bv 64 0xff)) (| (& (>> (var rs) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x17)) false)) (| (bv 64 0x3f800000) (var rs31))) (ite (== (& (>> (var rs) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1f)) false)) (bv 64 0x0)) (| (bv 64 0x40000000) (var rs31)) (let N (/. rna (fpos (var frs64)) (float 1 (bv 64 0x4000000000000000) )) (fbits (fneg (/. rna (var frs64) (pow rna (float 1 (bv 64 0x4010000000000000) ) (var N)))))))))) d "nop" f02000 0x0 nop -d "nsa a1, a2" 10e240 0x0 (seq (set ars (var a2)) (set sign (& (>> (var ars) (bv 32 0x1f) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (set a1 (ite (== (var sign) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1f)) false))) (bv 32 0x1f) (let b4 (== (var sign) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0xf)) false))) (let t3 (ite (var b4) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false)) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let b3 (== (var sign) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let t2 (ite (var b3) (& (>> (var t3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false)) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let b2 (== (var sign) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let t1 (ite (var b2) (& (>> (var t2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false)) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let b1 (== (var sign) (& (>> (var t1) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (let b0 (ite (var b1) (== (& (>> (var t1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign)) (== (& (>> (var t1) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign))) (- (| (<< (ite (var b4) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x4) false) (| (<< (ite (var b3) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x3) false) (| (<< (ite (var b2) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x2) false) (| (<< (ite (var b1) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1) false) (ite (var b0) (bv 32 0x1) (bv 32 0x0)))))) (bv 32 0x1))))))))))))) -d "nsau a1, a2" 10f240 0x0 (seq (set ars (var a2)) (set sign (bv 32 0x0)) (set a1 (ite (== (var sign) (var ars)) (bv 32 0x20) (let b4 (== (var sign) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let t3 (ite (var b4) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false)) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let b3 (== (var sign) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let t2 (ite (var b3) (& (>> (var t3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false)) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let b2 (== (var sign) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let t1 (ite (var b2) (& (>> (var t2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false)) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let b1 (== (var sign) (& (>> (var t1) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (let b0 (ite (var b1) (== (& (>> (var t1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign)) (== (& (>> (var t1) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign))) (| (<< (ite (var b4) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x4) false) (| (<< (ite (var b3) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x3) false) (| (<< (ite (var b2) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x2) false) (| (<< (ite (var b1) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1) false) (ite (var b0) (bv 32 0x1) (bv 32 0x0))))))))))))))))) +d "nsa a1, a2" 10e240 0x0 (seq (set ars (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (set sign (& (>> (var ars) (bv 32 0x1f) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (== (var sign) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1f)) false))) (bv 32 0x1f) (let b4 (== (var sign) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0xf)) false))) (let t3 (ite (var b4) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false)) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let b3 (== (var sign) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let t2 (ite (var b3) (& (>> (var t3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false)) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let b2 (== (var sign) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let t1 (ite (var b2) (& (>> (var t2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false)) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let b1 (== (var sign) (& (>> (var t1) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (let b0 (ite (var b1) (== (& (>> (var t1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign)) (== (& (>> (var t1) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign))) (- (| (<< (ite (var b4) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x4) false) (| (<< (ite (var b3) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x3) false) (| (<< (ite (var b2) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x2) false) (| (<< (ite (var b1) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1) false) (ite (var b0) (bv 32 0x1) (bv 32 0x0)))))) (bv 32 0x1))))))))))))) +d "nsau a1, a2" 10f240 0x0 (seq (set ars (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (set sign (bv 32 0x0)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (== (var sign) (var ars)) (bv 32 0x20) (let b4 (== (var sign) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let t3 (ite (var b4) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false)) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let b3 (== (var sign) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let t2 (ite (var b3) (& (>> (var t3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false)) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let b2 (== (var sign) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let t1 (ite (var b2) (& (>> (var t2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false)) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let b1 (== (var sign) (& (>> (var t1) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (let b0 (ite (var b1) (== (& (>> (var t1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign)) (== (& (>> (var t1) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign))) (| (<< (ite (var b4) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x4) false) (| (<< (ite (var b3) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x3) false) (| (<< (ite (var b2) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x2) false) (| (<< (ite (var b1) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1) false) (ite (var b0) (bv 32 0x1) (bv 32 0x0))))))))))))))))) d "oeq.s b2, f3, f1" 10232b 0x0 (seq (set b2 (! (|| (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (|| (<. (float 0 (var f3) ) (float 0 (var f1) )) (<. (float 0 (var f1) ) (float 0 (var f3) )))))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) d "ole.s b2, f3, f1" 10236b 0x0 (seq (set b2 (&& (! (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) )))) (! (<. (float 0 (var f1) ) (float 0 (var f3) ))))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) d "olt.s b2, f3, f1" 10234b 0x0 (seq (set b2 (&& (! (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) )))) (<. (float 0 (var f3) ) (float 0 (var f1) )))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) -d "or a2, a3, a1" 102320 0x0 (set a2 (| (var a3) (var a1))) +d "or a2, a3, a1" 102320 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (| (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "orb b2, b3, b1" 102322 0x0 (set b2 (|| (var b3) (var b1))) d "orbc b2, b3, b1" 102332 0x0 (set b2 (|| (var b3) (! (var b1)))) -d "quos a2, a3, a1" 1023d2 0x0 (set a2 (sdiv (var a3) (var a1))) -d "quou a2, a3, a1" 1023c2 0x0 (set a2 (div (var a3) (var a1))) -d "rems a2, a3, a1" 1023f2 0x0 (set a2 (smod (var a3) (var a1))) -d "remu a2, a3, a1" 1023e2 0x0 (set a2 (mod (var a3) (var a1))) +d "quos a2, a3, a1" 1023d2 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (sdiv (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "quou a2, a3, a1" 1023c2 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (div (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "rems a2, a3, a1" 1023f2 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (smod (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "remu a2, a3, a1" 1023e2 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (mod (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "rer a1, a2" 106240 0x0 nop -d "ret" 800000 0x0 (jmp (var a0)) -d "ret.n" 0df0 0x0 (jmp (var a0)) -d "retw" 900000 0x0 (seq (set n (& (>> (var a0) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (set nextPC (| (bv 32 0x0) (& (var a0) (bv 32 0x3fffffff)))) (set owb (var windowbase)) (set m (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x2)) (bv 32 0x2) (ite (== (var windowstart) (bv 32 0x3)) (bv 32 0x3) (bv 32 0x0))))) (branch (|| (== (var n) (bv 32 0x0)) (|| (&& (! (== (var m) (bv 32 0x0))) (! (== (var m) (var n)))) (|| (== (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x0)) (== (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1))))) nop (seq (branch (! (== (- (var windowstart) (| (bv 32 0x2) (var n))) (bv 32 0x0))) (set windowstart (bv 32 0x0)) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var owb) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set nextPC (ite (== (var n) (bv 32 0x1)) (var windowunderflow4) (ite (== (var n) (bv 32 0x2)) (var windowunderflow8) (var windowunderflow12)))))) (set windowbase (- (var windowbase) (| (bv 32 0x2) (var n)))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (var n) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (jmp (var nextPC))))) -d "retw.n" 1df0 0x0 (seq (set n (& (>> (var a0) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (set nextPC (| (bv 32 0x0) (& (var a0) (bv 32 0x3fffffff)))) (set owb (var windowbase)) (set m (ite (== (var windowstart) (bv 32 0x1)) (bv 32 0x1) (ite (== (var windowstart) (bv 32 0x2)) (bv 32 0x2) (ite (== (var windowstart) (bv 32 0x3)) (bv 32 0x3) (bv 32 0x0))))) (branch (|| (== (var n) (bv 32 0x0)) (|| (&& (! (== (var m) (bv 32 0x0))) (! (== (var m) (var n)))) (|| (== (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x0)) (== (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1))))) nop (seq (branch (! (== (- (var windowstart) (| (bv 32 0x2) (var n))) (bv 32 0x0))) (set windowstart (bv 32 0x0)) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var owb) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set nextPC (ite (== (var n) (bv 32 0x1)) (var windowunderflow4) (ite (== (var n) (bv 32 0x2)) (var windowunderflow8) (var windowunderflow12)))))) (set windowbase (- (var windowbase) (| (bv 32 0x2) (var n)))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (var n) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (jmp (var nextPC))))) +d "ret" 800000 0x0 (jmp (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "ret.n" 0df0 0x0 (jmp (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "retw" 900000 0x0 (seq (set n (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (set nextPC (| (bv 32 0x0) (& (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fffffff)))) (set owb (var windowbase)) (set m (ite (== (& (>> (var windowstart) (- (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)) (bv 32 0x1) (ite (== (& (>> (var windowstart) (- (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)) (bv 32 0x2) (ite (== (& (>> (var windowstart) (- (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)) (bv 32 0x3) (bv 32 0x0))))) (branch (|| (&& (! (== (var m) (bv 32 0x0))) (! (== (var m) (var n)))) (|| (== (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x0)) (== (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)))) nop (seq (branch (! (== (- (var windowstart) (| (bv 32 0x2) (var n))) (bv 32 0x0))) (set windowstart (bv 32 0x0)) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var owb) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set nextPC (ite (== (var n) (bv 32 0x1)) (var windowunderflow4) (ite (== (var n) (bv 32 0x2)) (var windowunderflow8) (var windowunderflow12)))))) (set windowbase (- (var windowbase) (| (bv 32 0x2) (var n)))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (var n) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (jmp (var nextPC))))) +d "retw.n" 1df0 0x0 (seq (set n (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (set nextPC (| (bv 32 0x0) (& (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fffffff)))) (set owb (var windowbase)) (set m (ite (== (& (>> (var windowstart) (- (var windowbase) (bv 32 0x1)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)) (bv 32 0x1) (ite (== (& (>> (var windowstart) (- (var windowbase) (bv 32 0x2)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)) (bv 32 0x2) (ite (== (& (>> (var windowstart) (- (var windowbase) (bv 32 0x3)) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)) (bv 32 0x3) (bv 32 0x0))))) (branch (|| (&& (! (== (var m) (bv 32 0x0))) (! (== (var m) (var n)))) (|| (== (& (>> (var ps) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x0)) (== (& (>> (var ps) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 32 0x1)))) nop (seq (branch (! (== (- (var windowstart) (| (bv 32 0x2) (var n))) (bv 32 0x0))) (set windowstart (bv 32 0x0)) (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x1) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set epc1 (bv 32 0x0)) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false))) (& (<< (var owb) (bv 32 0x8) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x8) false)))) (set nextPC (ite (== (var n) (bv 32 0x1)) (var windowunderflow4) (ite (== (var n) (bv 32 0x2)) (var windowunderflow8) (var windowunderflow12)))))) (set windowbase (- (var windowbase) (| (bv 32 0x2) (var n)))) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false))) (& (<< (var n) (bv 32 0x10) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false) (bv 32 0x10) false)))) (jmp (var nextPC))))) d "rfde" 003200 0x0 (jmp (ite (var ndepc) (var depc) (var epc1))) d "rfe" 003000 0x0 (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x0) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (jmp (var epc1))) d "rfi 2" 103200 0x0 (seq (set ps (var eps2)) (jmp (var epc2))) -d "rfr a1, f2" 4012fa 0x0 (set a1 (cast 32 false (var f2))) -d "rfwo" 003400 0x0 (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x0) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set windowstart (bv 32 0x0)) (set windowbase (& (>> (var ps) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (jmp (var epc1))) -d "rfwu" 003500 0x0 (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x0) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set windowstart (bv 32 0x1)) (set windowbase (& (>> (var ps) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (jmp (var epc1))) +d "rfr a1, f2" 4012fa 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (cast 32 false (var f2))) +d "rfwo" 003400 0x0 (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x0) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set windowstart (| (& (var windowstart) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (var windowbase) false))) (& (<< (bv 32 0x0) (var windowbase) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (var windowbase) false)))) (set windowbase (& (>> (var ps) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (jmp (var epc1))) +d "rfwu" 003500 0x0 (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x0) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (set windowstart (| (& (var windowstart) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (var windowbase) false))) (& (<< (bv 32 0x1) (var windowbase) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (var windowbase) false)))) (set windowbase (& (>> (var ps) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (jmp (var epc1))) d "rotw -1" f08040 0x0 (seq (set wb (+ (var windowbase) (bv 32 0xffffffff))) (set windowbase (var wb))) -d "round.s a2, f3, 1" 10238a 0x0 (seq (set fres (fround rna (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) )))) (set a2 (fbits (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) -d "rsil a1, 0xf" 106f00 0x0 (seq (set a1 (var ps)) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x0) false))) (& (<< (bv 32 0xf) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x0) false))))) +d "round.s a2, f3, 1" 10238a 0x0 (seq (set fres (fround rna (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) )))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (fbits (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) +d "rsil a1, 0xf" 106f00 0x0 (seq (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ps)) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x0) false))) (& (<< (bv 32 0xf) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x0) false))))) d "rsqrt0.s f1, f2" a012fa 0x0 nop -d "rsr a1, litbase" 100503 0x0 (set a1 (var litbase)) +d "rsr a1, litbase" 100503 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var litbase)) d "rsync" 102000 0x0 nop -d "rur.accx_0 a0" 0000e3 0x0 (set a0 (var accx_0)) -d "rur.accx_0 a1" 0010e3 0x0 (set a1 (var accx_0)) -d "rur.accx_1 a1" 1010e3 0x0 (set a1 (var accx_1)) -d "rur.qacc_h_0 a1" 2010e3 0x0 (set a1 (var qacc_h_0)) -d "rur.qacc_h_1 a1" 3010e3 0x0 (set a1 (var qacc_h_1)) -d "rur.qacc_h_2 a1" 4010e3 0x0 (set a1 (var qacc_h_2)) -d "rur.qacc_h_3 a1" 5010e3 0x0 (set a1 (var qacc_h_3)) -d "rur.qacc_h_4 a1" 6010e3 0x0 (set a1 (var qacc_h_4)) -d "rur.qacc_l_0 a1" 7010e3 0x0 (set a1 (var qacc_l_0)) -d "rur.qacc_l_1 a1" 8010e3 0x0 (set a1 (var qacc_l_1)) -d "rur.qacc_l_2 a1" 9010e3 0x0 (set a1 (var qacc_l_2)) -d "rur.qacc_l_3 a1" a010e3 0x0 (set a1 (var qacc_l_3)) -d "rur.qacc_l_4 a1" b010e3 0x0 (set a1 (var qacc_l_4)) -d "rur.gpio_out a1" c010e3 0x0 (set a1 (var gpio_out)) -d "rur.sar_byte a1" d010e3 0x0 (set a1 (var sar_byte)) -d "rur.fft_bit_width a1" e010e3 0x0 (set a1 (var fft_bit_width)) -d "rur.ua_state_0 a1" f010e3 0x0 (set a1 (var ua_state_0)) -d "rur.ua_state_1 a1" 0011e3 0x0 (set a1 (var ua_state_1)) -d "rur.ua_state_2 a1" 1011e3 0x0 (set a1 (var ua_state_2)) -d "rur.ua_state_3 a1" 2011e3 0x0 (set a1 (var ua_state_3)) -d "s8i a1, a2, 0xff" 1242ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0xff))) (store 0 (var vAddr) (cast 8 false (var a1)))) -d "s16i a1, a2, 0x1fe" 1252ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0x1fe))) (storew 0 (var vAddr) (cast 16 false (var a1)))) -d "s32c1i a1, a2, 0x3fc" 12e2ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0x3fc))) (set mem (loadw 0 32 (var vAddr))) (branch (== (var mem) (var scompare1)) (storew 0 (var vAddr) (var a1)) nop) (set a1 (var mem))) -d "s32e a1, a3, -0x38" 102349 0x0 (seq (set vAddr (+ (var a3) (bv 32 0xffffffc8))) (storew 0 (var vAddr) (var a1))) -d "s32i a1, a2, 0x3fc" 1262ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0x3fc))) (storew 0 (var vAddr) (var a1))) -d "sext a2, a3, 8" 102323 0x0 (set a2 (>> (cast 32 false (<< (var a3) (- (- (bv 32 0x20) (bv 32 0x8)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x8)) (msb (cast 32 false (<< (var a3) (- (- (bv 32 0x20) (bv 32 0x8)) (bv 32 0x0)) false))))) +d "rur.accx_0 a0" 0000e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0)) +d "rur.accx_0 a1" 0010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0)) +d "rur.accx_1 a1" 1010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_1)) +d "rur.qacc_h_0 a1" 2010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_0)) +d "rur.qacc_h_1 a1" 3010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_1)) +d "rur.qacc_h_2 a1" 4010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_2)) +d "rur.qacc_h_3 a1" 5010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_3)) +d "rur.qacc_h_4 a1" 6010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_4)) +d "rur.qacc_l_0 a1" 7010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_0)) +d "rur.qacc_l_1 a1" 8010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_1)) +d "rur.qacc_l_2 a1" 9010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_2)) +d "rur.qacc_l_3 a1" a010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_3)) +d "rur.qacc_l_4 a1" b010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_4)) +d "rur.gpio_out a1" c010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var gpio_out)) +d "rur.sar_byte a1" d010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar_byte)) +d "rur.fft_bit_width a1" e010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var fft_bit_width)) +d "rur.ua_state_0 a1" f010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_0)) +d "rur.ua_state_1 a1" 0011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_1)) +d "rur.ua_state_2 a1" 1011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_2)) +d "rur.ua_state_3 a1" 2011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_3)) +d "s8i a1, a2, 0xff" 1242ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0xff))) (store 0 (var vAddr) (cast 8 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) +d "s16i a1, a2, 0x1fe" 1252ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1fe))) (storew 0 (var vAddr) (cast 16 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) +d "s32c1i a1, a2, 0x3fc" 12e2ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fc))) (set mem (loadw 0 32 (var vAddr))) (branch (== (var mem) (var scompare1)) (storew 0 (var vAddr) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var mem))) +d "s32e a1, a3, -0x38" 102349 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0xffffffc8))) (storew 0 (var vAddr) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "s32i a1, a2, 0x3fc" 1262ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fc))) (storew 0 (var vAddr) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "sext a2, a3, 8" 102323 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (>> (cast 32 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x20) (bv 32 0x8)) (bv 32 0x0)) false)) (- (bv 32 0x20) (bv 32 0x8)) (msb (cast 32 false (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (- (- (bv 32 0x20) (bv 32 0x8)) (bv 32 0x0)) false))))) d "simcall" 005100 0x0 nop -d "slli a2, a3, 0x1f" 102301 0x0 (seq (set sa (bv 32 0x1f)) (set a2 (<< (var a3) (var sa) false))) -d "sll a1, a2" 0012a1 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (set a1 (<< (var a2) (var sa) false))) +d "slli a2, a3, 0x1f" 102301 0x0 (seq (set sa (bv 32 0x1f)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var sa) false))) +d "sll a1, a2" 0012a1 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var sa) false))) d "sqrt0.s f1, f2" 9012fa 0x0 nop -d "srai a2, a1, 1" 102121 0x0 (seq (set sa (bv 32 0x1)) (set a2 (>> (var a1) (var sa) (msb (var a1))))) -d "sra a2, a1" 1020b1 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (set a2 (>> (var a1) (var sa) (msb (var a1))))) -d "src a2, a3, a1" 102381 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (set a2 (cast 32 false (>> (append (var a3) (var a1)) (var sa) false)))) -d "srl a2, a1" 102091 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (set a2 (>> (var a1) (var sa) false))) -d "srli a2, a1, 1" 102141 0x0 (seq (set sa (bv 32 0x1)) (set a2 (>> (var a1) (var sa) false))) +d "srai a2, a1, 1" 102121 0x0 (seq (set sa (bv 32 0x1)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var sa) (msb (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))))) +d "sra a2, a1" 1020b1 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var sa) (msb (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))))) +d "src a2, a3, a1" 102381 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (cast 32 false (>> (append (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (var sa) false)))) +d "srl a2, a1" 102091 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x5)) false))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var sa) false))) +d "srli a2, a1, 1" 102141 0x0 (seq (set sa (bv 32 0x1)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (var sa) false))) d "ssai 1" 004140 0x0 (set sar (bv 32 0x1)) -d "ssa8l a1" 002140 0x0 (set sar (<< (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3) false)) -d "ssip f1, a2, 0x3fc" 13c2ff 0x0 (seq (set vAddr (var a2)) (storew 0 (var vAddr) (var f1)) (set a2 (bv 32 0x3fc))) -d "ssi f1, a2, 0x3fc" 1342ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0x3fc))) (storew 0 (var vAddr) (cast 32 false (var f1)))) -d "ssxp f2, a3, a1" 102358 0x0 (seq (set vAddr (var a3)) (storew 0 (var vAddr) (cast 32 false (var f2))) (set a3 (+ (var vAddr) (var a1)))) -d "ssx f2, a3, a1" 102348 0x0 (seq (set vAddr (+ (var a3) (var a1))) (storew 0 (var vAddr) (cast 32 false (var f2)))) -d "ssr a1" 000140 0x0 (seq (set sa (cast 5 false (var a1))) (set sar (cast 32 false (var sa)))) -d "ssl a1" 001140 0x0 (seq (set sa (cast 5 false (var a1))) (set sar (- (bv 32 0x20) (cast 32 false (var sa))))) -d "sub a2, a3, a1" 1023c0 0x0 (set a2 (- (var a3) (var a1))) +d "ssa8l a1" 002140 0x0 (set sar (<< (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3) false)) +d "ssip f1, a2, 0x3fc" 13c2ff 0x0 (seq (set vAddr (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 0 (var vAddr) (var f1)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (bv 32 0x3fc))) +d "ssi f1, a2, 0x3fc" 1342ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fc))) (storew 0 (var vAddr) (cast 32 false (var f1)))) +d "ssxp f2, a3, a1" 102358 0x0 (seq (set vAddr (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 0 (var vAddr) (cast 32 false (var f2))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (var vAddr) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) +d "ssx f2, a3, a1" 102348 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (storew 0 (var vAddr) (cast 32 false (var f2)))) +d "ssr a1" 000140 0x0 (seq (set sa (cast 5 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set sar (cast 32 false (var sa)))) +d "ssl a1" 001140 0x0 (seq (set sa (cast 5 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set sar (- (bv 32 0x20) (cast 32 false (var sa))))) +d "sub a2, a3, a1" 1023c0 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "sub.s f2, f3, f1" 10231a 0x0 (seq (set fres (-. rna (float 0 (var f3) ) (float 0 (var f1) ))) (set f2 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))))) -d "subx2 a2, a3, a1" 1023d0 0x0 (set a2 (- (<< (var a3) (bv 32 0x1) false) (var a1))) -d "subx4 a2, a3, a1" 1023e0 0x0 (set a2 (- (<< (var a3) (bv 32 0x2) false) (var a1))) -d "subx8 a2, a3, a1" 1023f0 0x0 (set a2 (- (<< (var a3) (bv 32 0x3) false) (var a1))) +d "subx2 a2, a3, a1" 1023d0 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1) false) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "subx4 a2, a3, a1" 1023e0 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x2) false) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "subx8 a2, a3, a1" 1023f0 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (- (<< (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3) false) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "syscall" 005000 0x0 nop -d "trunc.s a2, f3, 1" 10239a 0x0 (seq (set fres (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))) (set a2 (fcast_sint 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) +d "trunc.s a2, f3, 1" 10239a 0x0 (seq (set fres (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (fcast_sint 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) d "ueq.s b2, f3, f1" 10233b 0x0 (seq (set b2 (! (|| (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (|| (<. (float 0 (var f3) ) (float 0 (var f1) )) (<. (float 0 (var f1) ) (float 0 (var f3) )))))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) -d "float.s f2, a3, 1" 1023ca 0x0 (seq (set fres (fcast_float ieee754-bin32 rna (div (var a3) (bv 32 0x0)))) (set f2 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) +d "float.s f2, a3, 1" 1023ca 0x0 (seq (set fres (fcast_float ieee754-bin32 rna (div (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0)))) (set f2 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) d "ule.s b2, f3, f1" 10237b 0x0 (seq (set b2 (&& (! (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) )))) (! (<. (float 0 (var f1) ) (float 0 (var f3) ))))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) d "ult.s b2, f3, f1" 10235b 0x0 (seq (set b2 (&& (! (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) )))) (<. (float 0 (var f3) ) (float 0 (var f1) )))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) -d "umul.aa.ll a2, a1" 140270 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "umul.aa.hl a2, a1" 140271 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "umul.aa.lh a2, a1" 140272 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "umul.aa.hh a2, a1" 140273 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) -d "utrunc.s a2, f3, 1" 1023ea 0x0 (seq (set fres (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))) (set a2 (fcast_int 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) +d "umul.aa.ll a2, a1" 140270 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "umul.aa.hl a2, a1" 140271 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "umul.aa.lh a2, a1" 140272 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "umul.aa.hh a2, a1" 140273 0x0 (seq (set m1 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false))))) +d "utrunc.s a2, f3, 1" 1023ea 0x0 (seq (set fres (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (fcast_int 32 rna (var fres))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))))) d "un.s b2, f3, f1" 10231b 0x0 (seq (set b2 (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) )))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))))) d "waiti 0xf" 007f00 0x0 nop d "wdtlb a1, a2" 10e250 0x0 nop d "wer a1, a2" 107240 0x0 nop -d "wfr f1, a2" 5012fa 0x0 (set f1 (cast 64 false (var a2))) -d "wsr a1, lend" 100113 0x0 (set a1 (var lend)) -d "wsr a1, lcount" 100213 0x0 (set a1 (var lcount)) -d "wsr a1, sar" 100313 0x0 (set a1 (var sar)) -d "wsr a1, br" 100413 0x0 (set a1 (var br)) -d "wsr a1, litbase" 100513 0x0 (set a1 (var litbase)) -d "wsr a1, scompare1" 100c13 0x0 (set a1 (var scompare1)) +d "wfr f1, a2" 5012fa 0x0 (set f1 (cast 64 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) +d "wsr a1, lend" 100113 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lend)) +d "wsr a1, lcount" 100213 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lcount)) +d "wsr a1, sar" 100313 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar)) +d "wsr a1, br" 100413 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var br)) +d "wsr a1, litbase" 100513 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var litbase)) +d "wsr a1, scompare1" 100c13 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var scompare1)) d "witlb a1, a2" 106250 0x0 nop -d "wur.accx_1 a1" 1001f3 0x0 (set accx_1 (var a1)) -d "wur.qacc_h_0 a1" 1002f3 0x0 (set qacc_h_0 (var a1)) -d "wur.qacc_h_1 a1" 1003f3 0x0 (set qacc_h_1 (var a1)) -d "wur.qacc_h_2 a1" 1004f3 0x0 (set qacc_h_2 (var a1)) -d "wur.qacc_h_3 a1" 1005f3 0x0 (set qacc_h_3 (var a1)) -d "wur.qacc_h_4 a1" 1006f3 0x0 (set qacc_h_4 (var a1)) -d "wur.qacc_l_0 a1" 1007f3 0x0 (set qacc_l_0 (var a1)) -d "wur.qacc_l_1 a1" 1008f3 0x0 (set qacc_l_1 (var a1)) -d "wur.qacc_l_2 a1" 1009f3 0x0 (set qacc_l_2 (var a1)) -d "wur.qacc_l_3 a1" 100af3 0x0 (set qacc_l_3 (var a1)) -d "wur.qacc_l_4 a1" 100bf3 0x0 (set qacc_l_4 (var a1)) -d "wur.gpio_out a1" 100cf3 0x0 (set gpio_out (var a1)) -d "wur.sar_byte a1" 100df3 0x0 (set sar_byte (var a1)) -d "wur.fft_bit_width a1" 100ef3 0x0 (set fft_bit_width (var a1)) -d "wur.ua_state_0 a1" 100ff3 0x0 (set ua_state_0 (var a1)) -d "xsr a1, lend" 100161 0x0 (seq (set t0 (var a1)) (set a1 (var lend)) (set lend (var t0))) -d "xsr a1, lcount" 100261 0x0 (seq (set t0 (var a1)) (set a1 (var lcount)) (set lcount (var t0))) -d "xsr a1, sar" 100361 0x0 (seq (set t0 (var a1)) (set a1 (var sar)) (set sar (var t0))) -d "xsr a1, br" 100461 0x0 (seq (set t0 (var a1)) (set a1 (var br)) (set br (var t0))) -d "xsr a1, litbase" 100561 0x0 (seq (set t0 (var a1)) (set a1 (var litbase)) (set litbase (var t0))) -d "xsr a1, scompare1" 100c61 0x0 (seq (set t0 (var a1)) (set a1 (var scompare1)) (set scompare1 (var t0))) -d "xor a2, a3, a1" 102330 0x0 (set a2 (^ (var a3) (var a1))) +d "wur.accx_1 a1" 1001f3 0x0 (set accx_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_0 a1" 1002f3 0x0 (set qacc_h_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_1 a1" 1003f3 0x0 (set qacc_h_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_2 a1" 1004f3 0x0 (set qacc_h_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_3 a1" 1005f3 0x0 (set qacc_h_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_4 a1" 1006f3 0x0 (set qacc_h_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_0 a1" 1007f3 0x0 (set qacc_l_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_1 a1" 1008f3 0x0 (set qacc_l_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_2 a1" 1009f3 0x0 (set qacc_l_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_3 a1" 100af3 0x0 (set qacc_l_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_4 a1" 100bf3 0x0 (set qacc_l_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.gpio_out a1" 100cf3 0x0 (set gpio_out (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.sar_byte a1" 100df3 0x0 (set sar_byte (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.fft_bit_width a1" 100ef3 0x0 (set fft_bit_width (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.ua_state_0 a1" 100ff3 0x0 (set ua_state_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "xsr a1, lend" 100161 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lend)) (set lend (var t0))) +d "xsr a1, lcount" 100261 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lcount)) (set lcount (var t0))) +d "xsr a1, sar" 100361 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar)) (set sar (var t0))) +d "xsr a1, br" 100461 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var br)) (set br (var t0))) +d "xsr a1, litbase" 100561 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var litbase)) (set litbase (var t0))) +d "xsr a1, scompare1" 100c61 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var scompare1)) (set scompare1 (var t0))) +d "xor a2, a3, a1" 102330 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (^ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) d "xorb b2, b3, b1" 102342 0x0 (set b2 (^^ (var b3) (var b1)))