Suggestion: SPMP and Hypervisor extension

[sandro2pinto]

The current specification is ambiguous concerning the interaction of the SPMP with the Hypervisor extension.

The sentence describes that "there are extensions" that are being developed to support SPMP in a dual-stage model.

What are those "extensions"? The way I see it, it will be a single extension that will include part (or all) of the content that was removed recently in this commit:
185d2ee

Apart from polishing the jargon, I also suggest having a note with an updated roadmap status toward the formalization of such an extension (to provide clarity).

Btw, I have yet to see an open discussion on this model/profile where we may have virtualization without virtual memory (MMU) but rather based on a dual-stage sPMP. This is needed because many players don't understand the need for such a profile - this was pretty much corroborated by the recent comments provided by Qualcomm to the sPMP spec.

I will suggest Anup to add this topic to the agenda of the upcoming Hypervisor SIG meeting (25 Oct). I will also volunteer to prepare a few slides to drive the discussion and to share what is happening behind the scenes by some players and chip designers/manufacturers (to the extent I may disclose).