Invalid assignments in SV backend

[lexbailey]

I think there might be a bug in the SV generation. Below is an example from RISC-V.

I see generated code like the module below, where there is a few instances of the same problem.
For example: zz495_2 has type sail_unit, but then it is assigned the value {SAIL_UNIT, s_0}, which has the type {sail_unit, sail_unit}, which fails to type check.

module zinternal_errorzIB32zK(
    input sail_unit file_0 /* file */, 
    input logic [127:0] line_0 /* line */, 
    input sail_unit s_0 /* s */, 
    input bit zassert_reachablez3 /* assert_reachable */, 
    output logic [31:0] sail_return,
    output bit sail_have_exception /* have_exception */, 
    output t_exception sail_current_exception /* current_exception */
);
    sail_unit zz490_2;
    sail_unit zz492_2;
    sail_unit zz493_2;
    sail_unit zz494_2;
    sail_unit zz495_2;
    always_comb begin
        zz494_2 = sail_dec_str_zz5i(line_0);
        zz495_2 = {SAIL_UNIT, s_0};
        zz493_2 = {zz494_2, zz495_2};
        zz492_2 = {SAIL_UNIT, zz493_2};
        zz490_2 = {file_0, zz492_2};
        begin
            if (!zassert_reachablez3); else $fatal(zz490_2);
        end;
    end;
endmodule

Is this expected? It happens in lots of places in the code.