test.sus

module example_md {
	interface example_md : int[4] factors,
		int add_to ->
		int product, 
		int total

	reg int mul0 = factors[0] * factors[1]
	reg int mul1 = factors[2] * factors[3]

	reg product = mul0 * mul1
	reg total = product + add_to
}


// (a*b) + c
module multiply_add {
	interface multiply_add : int a, int b, int c -> int total

	reg int tmp = a * b
	total = tmp + c
}


module test_pow17 {
	int a = pow17(2)
}

module pow17 {
    interface pow17 : int i -> int o 
	    int i2  = i   * i
	reg int i4  = i2  * i2
	    int i8  = i4  * i4
	reg int i16 = i8  * i8
	        o   = i16 * i
}


module fibonnaci {
    interface fibonnaci : -> int num 
	state int cur = 1
	state int prev = 0

	
	num = cur + prev
	prev = cur
	cur = num
}

module blur2 {
	interface blur2 : int data, bool first -> int blurred
	
	state int prev

	if !first {
		blurred = data + prev
	}
	prev = data

	gen int a

	gen bool b = true
	gen bool bb = false

	if bb {
		a = 5
	} else {
		a = 3
	}
}


module Tree_Multiply {
    interface Tree_Multiply : int[4] values -> int total 
	reg int a = values[0] * values[1]
	reg int b = values[2] * values[3]
	reg total = a * b
}

module Accumulator {
    interface Accumulator : int term, bool done -> int total 
    state int tot
	initial tot = 0

    int new_tot = tot + term
    if done {
        reg total = new_tot
        tot = 0
    } else {
        tot = new_tot
    }
}


//timeline (a, true -> /) | (a, false -> /) .. (a, false -> r)* .. (a, true -> r)
module blur {
    interface blur : int a, bool done -> int result 
	state bool working
	initial working = false
	state int prev

	if working {
		reg reg reg result = prev + a // Add a pipeline stage for shits and giggles
	}
	prev = a
	working = !done
}



//timeline (X -> X) .. (/ -> X) .. (/ -> X) .. (/ -> X)
module Unpack4 {
    interface Unpack4 : int[4] packed -> int out_stream 
	gen int INITIAL = 0
	gen int A = 1
	

    state int st
	initial st = 0
    state int[3] stored_packed

    if st == INITIAL {
        out_stream = packed[0]
        stored_packed[0] = packed[1] // Shorthand notation is possible here "stored_packed[0:2] = packed[1:3]"
        stored_packed[1] = packed[2]
        stored_packed[2] = packed[3]
        st = 1
    } else if st == 1 {
        out_stream = stored_packed[0]
        st = 2
    } else if st == 2 {
        out_stream = stored_packed[1]
        st = 3
    } else if st == 3 {
        out_stream = stored_packed[2]
        st = INITIAL // Must restore initial conditions
        //finish // packet is hereby finished. 
    }
}

module generative {
    interface generative : int i -> int o, int o2 
	gen int x = 5
	gen int[x] ys

	//gen int[ys] zs

	gen int[3] ps

	gen int[x] a

	a[2] = 5
	a[1] = 2
	a[0] = 10
	gen int[3] xx = a

	gen bool test = true

	if test {i = 5}

	o = a[i]
	o2 = a[a[0]]
}

module add_indices_to_array {
	interface add_indices_to_array : int[10] values -> int[10] added_values

	for int i in 0..10 {
		int t = values[i]
		added_values[i] = t + i
	}
}

module assignment_producer {
    interface assignment_producer : -> int v'0, int o'0, bool j'0 }

module test_various_assignments {
	state int[3] st
	bool b
	reg int a, st[2], reg reg b = assignment_producer()
}

//timeline (bs -> /, true) | (bs -> v, false)
module first_bit_idx_6 {
    interface first_bit_idx_6 : bool[6] bits -> int first, bool all_zeros 
	if bits[0] {
		first = 0
		all_zeros = false
	} else if bits[1] {
		first = 1
		all_zeros = false
	} else if bits[2] {
		first = 2
		all_zeros = false
	} else if bits[3] {
		first = 3
		all_zeros = false
	} else if bits[4] {
		first = 4
		all_zeros = false
	} else if bits[5] {
		first = 5
		all_zeros = false
	} else {
		all_zeros = true
	}

	/*first int i in 0..6 where bits[i] {
		first = i
		all_zeros = false
	} else {
		all_zeros = true
	}*/

}

module multiply_add_with_latencies {
    interface multiply_add_with_latencies : int a'0, int b'0, int c'0 -> int r'0 
    int tmp'1 = multiply(a, b)
	reg r = tmp + c
}

module first_bit_idx_24 {
    interface first_bit_idx_24 : bool[24] bits -> int first 
	int[4] offsets
	bool[4] was_nonzeros

	for int i in 0..4 {
		bool[6] these_bits
		for int j in 0..6 {
			these_bits[j] = bits[i * 6 + j]
		}
		
		int offset, bool was_nonzero = first_bit_idx_6(these_bits)
		offsets[i] = offset
		was_nonzeros[i] = was_nonzero
	}
}

module permute {
    interface permute : bool[128] mbf, int selected_permutation -> bool[128] permuted_mbf 
	// cvt_to_double
	permuted_mbf = mbf
}

//timeline (X, [false24], true -> /, false) | (X, vs, true -> X, true) .. (/, /, false -> X, true)*
module permute24 {
    interface permute24 : bool[128] mbf, bool[24] valid_permutes, bool start -> bool[128] permuted_out, bool permuted_out_valid 
	state bool[128] stored_mbf
	state bool[24] stored_valid_permutes = 000000000000000000000000

	gen int aaaaa = 5


	bool[24] permutes_to_keep
	permutes_to_keep[0] = false
	for int i in 1..24 {
		permutes_to_keep[i] = permutes_to_keep[i-1] | stored_valid_permutes[i-1]
	}

	int current_permutation_idx = first_bit_idx_24(permutes_to_keep)
	
	stored_valid_permutes = stored_valid_permutes & permutes_to_keep

	permuted_out = permute(stored_mbf, current_permutation_idx)

	aaaaa()
}



module test_single_wire {
    interface test_single_wire : int a -> int o 
	o = a
}

module disjoint_ports {
    interface disjoint_ports : int a, int b, int c -> int result 
	reg result = a + b
	// don't touch c
}

module undeteriminable_input_latency {
    interface undeteriminable_input_latency : int a, int b -> int x, int y 
	reg int a_d = a
	int t = a_d + b
    reg reg reg int a_dd = a
	reg int t_d = t
    x = t_d + a_dd
    y = t
}

module specified_input_latency {
    interface specified_input_latency : int a'0, int b'1 -> int x, int y 
	reg int a_d = a
    int t = a_d + b
    reg reg reg int a_dd = a
	reg int t_d = t
    x = t_d + a_dd
    y = t
}

module determinable_input_latency {
    interface determinable_input_latency : int a, int b -> int x, int y 
	reg int a_d = a
    int t = a_d + b
    reg reg int a_dd = a
	reg int t_d = t
    x = t_d + a_dd
    y = t
}

// This module is a copy of ::undeteriminable_input_latency, but it doesn't have an error, because we just assume the latency of the inner nodes to be the earliest possible. 
module determinable_because_no_input_output_ports {
    interface determinable_because_no_input_output_ports : int a -> int x 
	reg int a_d = a
    int t = a_d
    reg reg reg int a_dd = a
	reg int t_d = t
    x = t_d + a_dd
}

// This module is a copy of ::undeteriminable_input_latency, but it doesn't have an error, because we just assume the latency of the inner nodes to be the earliest possible. 
module conflicting_latency_declarations {
    interface conflicting_latency_declarations : int a'0 -> int x'1 
	reg int nio = a
	reg x = nio
}

module bad_cycle {
    interface bad_cycle : int a -> int r 
	state int state_reg
	initial state_reg = 0

	r = state_reg

	reg state_reg = state_reg + a
}

module module_taking_time {
	interface module_taking_time : int i'0 -> int o'5
	o = i
}

module matrix_vector_mul {
	interface matrix_vector_mul : 
		int[30][20] mat, int[20] vec -> int[30] result
	
	for int row in 0..30 {
		int[20] row_products
		for int col in 0..20 {
			row_products[col] = mat[row][col] * vec[col]
		}
		result[row] = +row_products
	}
}

module bad_cycle2 {
    interface bad_cycle2 : int a -> int r 
	state int test
	initial test = 0

	test = module_taking_time(test+a)

	r = test
}

module module_taking_a_lot_of_time {
    interface module_taking_a_lot_of_time : int data_in'0 -> int data_out'200 
	data_out = data_in
}


/*extern*/ module offset_latency {
    interface offset_latency : int i'0 -> int o'-5 

}



module good_cycle {
    interface good_cycle : int a -> int r 
	state int test
	initial test = 0
	
	int new_test = test + a
	test = new_test

	r = new_test
}

module input_only {
    interface input_only : int i 
	state int loop
	initial loop = 0
	loop = loop + i
}

module multiple_inputs_only {
    interface multiple_inputs_only : int i, int i2 
	state int loop
	initial loop = 0
	loop = loop + i + i2
}

module output_only {
    interface output_only : -> int o 
	state int loop
	initial loop = 0
	loop = loop + 1
	reg o = loop
}

module multiple_outputs_only {
    interface multiple_outputs_only : -> int o, int o2 
	state int loop
	initial loop = 0
	loop = loop + 1
	reg o = loop
	reg reg o2 = loop
}


// Test submodule comment
module submodule {
    interface submodule : int a, int b -> int r 
	r = a * b
}

// module doing nothing
module doNothing {}

/*
Multiline

comment

# Test Title

*/
module contains_submodule_submodule {
    interface contains_submodule_submodule : int a, int b, int c -> int r 
	// Temp val
    int tmp = submodule(a, b)
	doNothing()
	reg r = tmp + c
}


module xor {
    interface xor : bool x1, bool x2 -> bool y 
	bool w1 = !x1
	bool w2 = !x2

	bool w3 = x1 & w2
	bool w4 = x2 & w1

	y = w3 | w4
}

module use_xor {
	bool b = xor(true, false)
}

module fizz_buzz {
    interface fizz_buzz : int v -> int fb 
	gen int FIZZ = 888
	gen int BUZZ = 555
	gen int FIZZ_BUZZ = 888555
	
	bool fizz = v % 3 == 0
	bool buzz = v % 5 == 0
	
	if fizz & buzz {
		fb = FIZZ_BUZZ
	} else if fizz {
		fb = FIZZ
	} else if buzz {
		fb = BUZZ
	} else {
		fb = v
	}
}

module fizz_buzz_gen {
    interface fizz_buzz_gen : int v -> int fb 
	gen int FIZZ = 888
	gen int BUZZ = 555
	gen int FIZZ_BUZZ = 888555
	gen int TABLE_SIZE = 256

	gen int[TABLE_SIZE] lut
	
	for int i in 0..TABLE_SIZE {
		gen bool fizz = i % 3 == 0
		gen bool buzz = i % 5 == 0
		
		gen int tbl_fb
		if fizz & buzz {
			tbl_fb = FIZZ_BUZZ
		} else if fizz {
			tbl_fb = FIZZ
		} else if buzz {
			tbl_fb = BUZZ
		} else {
			tbl_fb = i
		}

		lut[i] = tbl_fb
	}

	fb = lut[v]
}

module mbf_dual {
    interface mbf_dual : bool[128] mbf -> bool[128] dual 
	for int i in 0..128 {
		dual[i] = !mbf[127-i]
	}
}


module monotonize_down {
    interface monotonize_down : bool[16] mbf -> bool[16] mtDown 
	bool[16] mbf2
	bool[16] mbf4
	bool[16] mbf8
	
	for int i in 0..16 {
		if i % 2 == 0 {
			mbf2[i] = mbf[i] | mbf[i+1]
		} else {
			mbf2[i] = mbf[i]
		}
	}

	for int i in 0..16 {
		if i % 4 < 2 {
			mbf4[i] = mbf2[i] | mbf2[i+2]
		} else {
			mbf4[i] = mbf2[i]
		}
	}
	
	for int i in 0..16 {
		if i % 8 < 4 {
			mbf8[i] = mbf4[i] | mbf4[i+4]
		} else {
			mbf8[i] = mbf4[i]
		}
	}
	
	for int i in 0..16 {
		if i % 16 < 8 {
			mtDown[i] = mbf8[i] | mbf8[i+8]
		} else {
			mtDown[i] = mbf8[i]
		}
	}
}

module my_mod {
    interface my_mod : int i -> bool a, bool b 
	a = i == 3
	b = i == 5
}

module use_my_mod {
    interface use_my_mod : -> bool either 
	bool x, bool y = my_mod(3)

	either = x | y
}

// Main module documentation
module submodule_named_ports {
    interface submodule_named_ports : int port_a, int port_b -> int port_c 
	port_c = port_a + port_b

	
}

module use_submodule_named_ports {
    interface use_submodule_named_ports : int i -> int o 
// Test submodule documentation
	submodule_named_ports sm

	o = sm(i, i)

	sm.port_a = i

	sm.port_b = i

	o = sm.port_c
}

module contains_submodule_submodule {
    interface contains_submodule_submodule : int a, int b, int c -> int r 
	// Temp val
    int tmp = submodule(a, b)
	doNothing()
	reg r = tmp + c
}



module cross_bool {
	interface in : bool i'0
	interface out : -> bool o'0
	o = true
}
module cross_int {
	interface in : int i'0
	interface out : -> int o'0
	o = 1
}

module cross_memory {
	interface in : bool[20][512] i'0
	interface out : -> bool[20][512] o'0
	o[0][0] = true
}

module offset_backwards {
    interface offset_backwards : bool i'0 -> bool o'-5 
	o = true
}

module dual_port_mem {
	state bool[20][512] mem

	interface write : bool write, bool[20] wr_data, int wr_addr

	interface read : bool read, int rd_addr -> bool[20] rd_data

	if write {
		mem[wr_addr] = wr_data
	}

	cross_memory cr_m
	cr_m.i = mem
	if read {
		rd_data = cr_m.o[rd_addr]
	}
}

module use_fifo {
    interface use_fifo : -> int o 
	FIFO fiii

	bool[20] data

	bool valid, bool[20] data2 = fiii.pop(true)

	//bool ready = fiii.push(valid, data2)
}

module test_separated_domain {
    interface test_separated_domain : int main 
	int domain2

	int domain3

	int domain4

	cross_int ci
	ci.i = domain3
	domain4 = ci.o

	int domain5

	int #(MIN: 0, MAX: 199) my_int
}

module no_port_module {}

module use_no_input_module {
	no_port_module()

	no_port_module no_port
	int x = no_port()
}

module mod_with_unused_interface {
	if false {
		interface v : int a -> int b
	}
}

module test_write_to_gen_var {
	int a

	gen int b

	a = b

	a = a

	b = b

	b = a
}

module use_bad_interface {
	mod_with_unused_interface mm

	mm.a

	// ICE(not yet implemented: Type Unification Unknown Named(type_1)): mm.a = 5
}

/*
	interface
	action
	query
	trigger
*/

// TODO valid and index should be part of a separate 'interface'
module sequenceDownFrom {
	//interface sequence : -> 

	interface start : bool start'0, int upTo'0

	output bool ready'0

	interface iter : -> bool valid, state int index

	cross_bool start_cr
	start_cr.i = start
	
	cross_int upTo_cr
	upTo_cr.i = upTo

	cross_bool ready_cr
	ready = ready_cr.o

	valid = index != 0
	ready_cr.i = !valid
	if valid {
		index = index - 1
	}

	if start_cr.o {
		index = upTo_cr.o
	}
}

module sumUpTo {
    interface sumUpTo : bool start 

	sequenceDownFrom sdf

	sdf.start(start, 20)

	bool re = sdf.ready

	bool iter_valid, int iter_index = sdf.iter()
	if iter_valid {
		int idx = iter_index
	}

	int beep
}

module test #(T, int MY_INPUT) {
    interface test : ::int #(beep: 20 > 3, BEEP: int) ab 

	MY_INPUT = 3

	input int beep

	beep = 3

	FIFO #(BITWIDTH: 4) badoop
}

module use_test {
	test #(MY_INPUT: 3) test_mod


}


module tinyTestMod #(int beep) {
	output int o = beep
}


module testTinyTestMod {
	tinyTestMod #(beep: 3) a
	tinyTestMod #(beep: 4) b
	tinyTestMod #(beep: 3) c
}



module tree_add #(int WIDTH) {
	input int[WIDTH] values
	output int sum

	if WIDTH == 1 {
		sum = values[0]
	} else {
		gen int HALF_WIDTH = WIDTH / 2
		tree_add #(WIDTH: HALF_WIDTH) left
		tree_add #(WIDTH: HALF_WIDTH) right

		for int i in 0..HALF_WIDTH {
			left.values[i] = values[i]
			right.values[i] = values[i+HALF_WIDTH]
		}

		if WIDTH % 2 == 0 {
			reg sum = left.sum + right.sum
		} else {
			reg sum = left.sum + right.sum + values[WIDTH - 1]
		}
	}
}

module make_tree_add {
	gen int SIZE = 255

	int[SIZE] vs

	for int i in 0..SIZE {
		vs[i] = i
	}

	tree_add #(WIDTH: SIZE) tr

	tr.values = vs

	output int beep = tr.sum
}


module replicate #(T, int NUM_REPLS) {
	input T data

	output T[NUM_REPLS] result

	for int i in 0..NUM_REPLS {
		result[i] = data
	} 
}

module use_replicate {
	//replicate #(NUM_REPLS: 50, NUM_REPLS: 30, T: type bool) a
	replicate #(NUM_REPLS: 20, T: type int[30]) b
	replicate c

	int val = 3

	c.data = val
	int[30] out = c.result
}

module permute_t #(T, int SIZE, int[SIZE] SOURCES) {
	interface permute : T[SIZE] d_in -> T[SIZE] d_out

	for int i in 0..SIZE {
		d_out[i] = d_in[SOURCES[i]]
	}
}

module use_permute {
	gen int[8] SOURCES

	SOURCES[0] = 3
	SOURCES[1] = 2
	SOURCES[2] = 4
	SOURCES[3] = 5
	SOURCES[4] = 1
	SOURCES[5] = 2
	SOURCES[6] = 7
	SOURCES[7] = 6


	int[2] inArr

	inArr[0] = 2387
	inArr[1] = 786823

	permute_t #(SIZE: 8, SOURCES, T: type int) permut

	int[8] beep = permut.permute(SOURCES)
}

module instruction_decoder {
	interface from : bool[32] instr
	interface is_jump
	interface is_load
	interface is_arith
	
}

module run_instruction {
    interface run_instruction : bool[32] instr 
	instruction_decoder decoder
	decoder.from(instr)

	if decoder.is_jump() : int target_addr {
		// ...
	}
	if decoder.is_load() : int reg_to, int addr {
		// ...
	}
	if decoder.is_arith() : int reg_a, int reg_b, Operator op {
		// ...
	}
}

// Test no main interface error
module no_main_interface {
	//interface no_main_interface
}

module use_no_main_interface {

	no_main_interface no_interface_named
	int x = no_interface_named()
	int y = no_main_interface()
}

module moduleWithBadDeclaration {
	int[true] a
}

module moduleWithBadInterface {
	interface moduleWithBadInterface : int[true] a
}

module useModuleWithBadInterface {
	int[3] xyz
	moduleWithBadInterface(xyz)

	xyz[3] = true
}


const int SUM_UP #(int SIZE, int[SIZE] DATA) {
	SUM_UP = 0
	for I in 0..SIZE {
	    SUM_UP = SUM_UP + DATA[I]
	}
}

__builtin__ const T dont_care #(T) {}

module m {
	gen int[5] DATA
	DATA[0] = 2
	DATA[1] = 2
	DATA[2] = 2
	DATA[3] = 2
	DATA[4] = 5

	gen int X = SUM_UP #(SIZE: 4, DATA, BEEEP: 3)

	int #(ABC) x
}

module xyz {
	int[5] a

	CrossDomain cr

	cr.in = a
	int[5] b = cr.out
}

module numbersToAddUp {
	int[5] arr
	arr[0] = 3
	arr[1] = 3
	arr[2] = 3
	arr[3] = 3
	arr[4] = 3

	// Don't need to specify #(WIDTH: 5)!
	TreeAdd adder
	int total = adder(arr)
}


/// Test parametrized extern modules
// Expects a SV module of the form:
/*
```sv
module sized_int_add #(
	parameter int LEFT_SIZE,
	parameter int RIGHT_SIZE,
	parameter int OUTPUT_SIZE
) (
	input clk,
	input[LEFT_SIZE-1:0] a,
	input[RIGHT_SIZE-1:0] b,
    // c is output 1 cycle after a and b are provided
	output[OUTPUT_SIZE-1:0] c
);
```
*/
extern module sized_int_add #(int LEFT_SIZE, int RIGHT_SIZE, int OUTPUT_SIZE) {
	interface sized_int_add : bool[LEFT_SIZE] a'0, bool[RIGHT_SIZE] b'0 -> bool[OUTPUT_SIZE] c'1
}

module use_sized_int_add {
	interface use_sized_int_add : bool[4] a, bool[3] b -> bool[5] c

	c = sized_int_add(a, b)
}


module implicit_domain_forbidden {
	input int bad_port

	domain bad_domain

	output int port_after_domain
}

module conflicting_domain_with_port_name {
	domain my_domain
	input int my_domain

	domain my_domain
}