From b0b8760386a870898863c2957bce03069bd65820 Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 25 Nov 2024 10:33:58 -0500 Subject: [PATCH] implementation for store half instruction in riscv32im --- .../src/interpreters/riscv32im/interpreter.rs | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 0ec3dd0807..bc9aef00f2 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -1999,7 +1999,26 @@ pub fn interpret_stype(env: &mut Env, instr: SInstruction) env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32)); } SInstruction::StoreHalf => { - unimplemented!("StoreHalf") + // sh: M[x[rs1] + sext(offset)] = x[rs2][15:0] + let [v0, v1] = [ + { + let value_scratch = env.alloc_scratch(); + unsafe { env.bitmask(&local_rs2, 8, 0, value_scratch) } + }, + { + let value_scratch = env.alloc_scratch(); + unsafe { env.bitmask(&local_rs2, 16, 8, value_scratch) } + }, + ]; + + env.lookup_8bits(&v0); + env.lookup_8bits(&v1); + + env.write_memory(&address, v0); + env.write_memory(&(address.clone() + Env::constant(1u32)), v1); + + env.set_instruction_pointer(next_instruction_pointer.clone()); + env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32)); } SInstruction::StoreWord => { unimplemented!("StoreWord")