From 911df441c2b861026c5f3935a6e258be367ca203 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 15:13:19 +0100 Subject: [PATCH] o1vm/riscv32im: add tests for addi with negative values --- .../programs/riscv32im/bin/addi_negative | Bin 0 -> 456 bytes .../programs/riscv32im/src/addi_negative.S | 22 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 18 ++++++++++++++ 3 files changed, 40 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/addi_negative create mode 100644 o1vm/resources/programs/riscv32im/src/addi_negative.S diff --git a/o1vm/resources/programs/riscv32im/bin/addi_negative b/o1vm/resources/programs/riscv32im/bin/addi_negative new file mode 100755 index 0000000000000000000000000000000000000000..f610f7df86b0c65ba290b0ec29a2b2bf9aab3055 GIT binary patch literal 456 zcma)2F;2rk5M0|yh(rUr4V>+_vN_pn2^yVO=! z^Q_d>EHiW~UFqzRgfGkOW=>;F`P`a~^EsSI>eoKFV3v}GVjm=J z?n+Gv&Mvp1;6MBqrx@suXR0L2wOm=SRfGRLMtVLn}soOKyevDYKPVA6Mgdq::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 100); + assert_eq!(witness.registers[T1], 50); + assert_eq!(witness.registers[T2], (-50_i32) as u32); +}