[FIRRTL] Incorrect directory behavior when testbench involved

[seldridge]

Consider the following FIRRTL:

FIRRTL version 4.1.0
circuit Foo: %[[
  {
    "class": "firrtl.transforms.DontTouchAnnotation",
    "target": "~Foo|Baz>a"
  },
  {
    "class": "sifive.enterprise.firrtl.TestBenchDirAnnotation",
    "dirname": "testbench/"
  },
  {
    "class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
    "target": "~Foo|Bar"
  }
]]
  layer A, bind, "internal":

  module Baz:
    wire a: UInt<1>
    invalidate a

  module Bar:

    layerblock A:
      inst baz of Baz

  public module Foo:

    inst bar of Bar
    inst baz of Baz

When compiled this produces the following Verilog:

// Generated by CIRCT firtool-1.99.2-40-g4e478778c-dirty
module Bar();
endmodule


// ----- 8< ----- FILE "internal/layers-Foo-A.sv" ----- 8< -----

// Generated by CIRCT firtool-1.99.2-40-g4e478778c-dirty
`ifndef layers_Foo_A
`define layers_Foo_A
bind Bar Bar_A a ();
`endif // layers_Foo_A

// ----- 8< ----- FILE "testbench/Baz.sv" ----- 8< -----

// Generated by CIRCT firtool-1.99.2-40-g4e478778c-dirty
// VCS coverage exclude_file
module Baz();
  wire a = 1'h0;
endmodule


// ----- 8< ----- FILE "internal/Bar_A.sv" ----- 8< -----

// Generated by CIRCT firtool-1.99.2-40-g4e478778c-dirty
// VCS coverage exclude_file
module Bar_A();
  Baz baz ();
endmodule


// ----- 8< ----- FILE "testbench/Foo.sv" ----- 8< -----

// Generated by CIRCT firtool-1.99.2-40-g4e478778c-dirty
// VCS coverage exclude_file
module Foo();
  Bar bar ();
  Baz baz ();
endmodule

Baz is instantiated by both the testbench and a layer block. This should cause Baz to be put in the LCA of their directories (LCA("./testbench/", "./internal/") == "./"). However, this is instead put into testbench/.

What I think is going on is that the testbench directory handling is being done in LowerToHW while the layer directory handling is being done earlier in AssignOutputDirs. The testbench directory information should be handled in the earlier pass.