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ECP5 Versa Board PCIe #364

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RArbore opened this issue Mar 11, 2022 · 4 comments
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ECP5 Versa Board PCIe #364

RArbore opened this issue Mar 11, 2022 · 4 comments
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@RArbore
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RArbore commented Mar 11, 2022

Hello,

I'm wondering whether the ECP5 Versa evaluation board is supported via Litex w/ PCIe? I see that it is on the board list for this repo, but I don't see it mentioned anywhere on the litepcie repo - there is an issue related to it, but it didn't seem like it got resolved (enjoy-digital/litepcie#20). If not, is the fully open toolchain for Artix 7 chips mature enough to the point where I could create a PCIe design with an Artix 7 board using just open tools?

@enjoy-digital
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Hello @RArbore,

LitePCIe is not supported on the ECP5 Versa (as you saw due to the lack of PCIe PHY). The F4PGA team has already been able to use GTP transceivers with Xilinx Artix7 (https://antmicro.com/blog/2021/12/sata-with-open-source-fpga-tools/) but integrating PCIe was one of the next plans IIRC. So this is not yet available but is not too unrealistic in a near future.

Another future option for PCIe could be the Lattice Certus-NX versa board that should have good open-source toolchain suport and hardened PCIe PHY. It's possible that LitePCIe support will be added to these devices in a near future.

@RArbore
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RArbore commented Mar 16, 2022

Hello,

Once F4PGA adds PCIe support for the GTP transceivers, would LitePCIe work with F4PGA as a fully open toolchain at that point? Also, I saw in the source tree that there are some PCIe verilog modules that appear to be copyrighted by Xilinx. Are those necessary for LitePCIe to work? I would prefer not to have to use them since they are not FOSS.

@enjoy-digital
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enjoy-digital commented Mar 16, 2022

The Xilinx files are mostly wrappers around the transceivers and PCIe Hard block. Some equivalent code would need to be created if you don't want to use them. This is not something we planned but the effort could be evaluated if you want to fund such work. If F4FPGA add sPCIe support, it will probably by reusing the Xilinx files.

@enjoy-digital
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The question has been answered, closing.

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